Timing Example Of Multiplexed Bus - Fujitsu MB88121 Application Note

3.1.3.5 Timing example of multiplexed bus

An example with configuration ACR_TYP[3:0]=7 and AWR=0x0008 is shown below.
Note:
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The basic access cycle includes 2 address output cycles and 1 data cycle.
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In the address output cycles pin ASX (address strobe) is asserted.
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Set one as the burst length (register ACR_BST[1:0]=0).
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Like the ordinary bus register AWR[15:12], AWR[7:4], AWR[2:0] can be set.
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Pin RDY (ACR_TYP0=1) is enabled for external wait insertion
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Use pin WEX as the write strobe (ACR_TYP1=1)
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Interfacing MB91460 TO MB88121
Chapter 3 Software
Figure 3-6 Timing example of the multiplexed bus mode
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