System Architecture - Analog Devices ADSP-21262 EZ-KIT Lite Manual

System Architecture

System Architecture
3-2
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This section describes the processor's configuration on the EZ-KIT Lite
board.
JTAG
Header
SRAM
25 MHz
Oscillator
Reset PB
SPI
A5V 3.3V 1.2V
Power Regulation
SPI FLASH
Figure 3-1. System Architecture Block Diagram
The EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-21262 DSP. The DSP core is powered at 1.2V, and the IO is pow-
ered at 3.3V. Two 0-ohm resistors give access to the DSP's power planes
and allow to measure the power consumption of the processor. The
resistor provides access to the IO voltage of the processor, and the
resistor provides access to the core voltage plane of the processor.
ADSP-21262 EZ-KIT Lite Evaluation System Manual
GP LEDs 512k x 8
(8) SRAM
Par allel
Port
ADSP-21262
DSP
FLAG0-3 DAI
AD1835
CODEC
2 2
Stereo In RCA Stereo Out RCA
PBs (4)
Jacks (2x1) J acks (4x2)
1M x 8
Flash
Expa nsion
Conn ector s
Type A
CS8416
Phono
SPDIF RX
Headphone
Jack
R79
R80