Pin Assignment; Ecu Interface Connector Con1 (Jtag Mode); Fig. 7-3 Location Of The Fetk-S1.1 Interfaces - ETAS FETK-S1.1 User Manual

Emulator probe for infineon aurix mcu family
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ETAS
7.10

Pin Assignment

Fig. 7-3
7.10.1

ECU Interface Connector CON1 (JTAG Mode)

Pin
Signal
1
DAP0
8
DAP1
4
DAP2
2
/TRST
10
RESERVED (TDI) Output
11
/ESR0
13
/PORST
5
WDGDIS
18
GATE_PORST
7
VDDP (Sense)
3, 6,
GND
9, 12,
20
14,
DNU
16
19
DAPE0
17
DAPE1
15
DAPE2
FETK-S1.1 - User's Guide
CON2
CON1
Location of the FETK-S1.1 Interfaces
Direction
Output
Bidir
Bidir
Output
Bidir
Bidir
Output
Input
Input
Power
Output
Output
Bidir
Bidir
CON3
Comment
DAP signal
DAP signal
DAP signal
DAP signal
Reserved
ECU reset signal (open drain) for reset
assertion and supervision
ECU power on reset signal (open drain)
for reset assertion and supervision
Watchdog disable signal
Overwrite /PORST status at power on,
0 V = /PORST inactive, 3.3 V = active
Sense for switched power supply of
ECU (ignition)
Signal ground
DNU, Mfr test signal
DAPE signal
DAPE signal
DAPE signal
Technical Data
44

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