Microcontroller Interface; Test Characteristics; Dap Timing Characteristics - ETAS FETK-S1.1 User Manual

ETAS
7.6

Microcontroller Interface

ECU Standby
RAM Output Volt-
age
VDDPSTBY
Output Voltage
Cal_Wakeup
Output Voltage
ECU Power Sup-
ply Supervision
Voltage
(3.3 V selected)
ECU Standby
RAM Supervision
Voltage
(1.25 V selected)
7.7

Test Characteristics

Parameter
Start Up Time 1
Start Up Time 2
1)
/PORST is not pulled low until FETK start up time
7.8

DAP Timing Characteristics

The FETK-S1.1 supports two DAP modes:
• 2-pin DAP mode: one data pin (direction via protocol), one clock pin
• 3-pin DAP mode: two data pins (bidirectional, direction via protocol), one
clock pin
The 2-pin DAP mode is the FETK-S1.1 DAP interface default mode.
NOTE
DAP timing parameters in this chapter refer to the DAP interface (CON1) of
the FETK-S1.1. The DAP wiring to the ECU (ETAM1) must be taken account
additionally.
All timings are measured at a reference level of 1.5 V. Output signals are mea-
sured with 20 pF to ground and 50  to 1.5 V.
FETK-S1.1 - User's Guide
Symbol Condition
VDDSTBY max. 500 mA
load
VDDP- max. 80 mA load 3.14
STBY
CAL_WAK U = 6 - 36 V;
Batt
EUP load = 0 - 50 mA
VDDP ECU on
ECU off
IDDP VDDP 3.3 V
VDDSTBY 
VDDSTBY
/VDDST-
VDDSTBY 
BY_SENSE
IDDSTBY VDDSTBY 1.30 V
Symbol Condition
1)
t U = 12 V
startup1 Batt
ECU_VDDP goes
high
1)
t U goes high
startup2 Batt
Technical Data
Min Typ Max Unit
1.27 1.32 1.36 V
3.3 3.46 V
U - U
Batt Batt
1 V
2.67 2.77 2.89 V
2.44 2.56 2.68 V
800
1.03 1.07 1.1
1.02 1.06 1.08 V
50
Min Typ Max Unit
0 6 ms
180 670 ms
V
A
V
A
40