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Clock
The clock connectors allow for a connection point to the SYS_CLKIN0 and SYS_CLKIN1 input pins of the
processor. Two other clocks are generated - FPGA_CLK0 and FPGA_CLK1 which are used to drive any CPLD or
FPGA devices that may be connected to the external connector. The clocks are fixed at 30MHz and 16MHz
respectively. The 30MHz oscillator drives the Arm Cortex M4 processor while the 16MHz drives the Arm Cortex M0
processor. The 30MHz oscillator results in system clocks of 100MHz or multiples of this. This allows for PWM
frequencies of integer divides of 100MHz, e.g., 100KHz or 50Khz. For various other frequencies, like 90MHz system
clock resulting in PWM's of 45KHz, it is possible the 30MHz oscillator may need to be changed to a 25MHz
oscillator for example. Please see the Hardware reference manual for PLL details and calculations.
Figure 10: Clock Buffer Circuit
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