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CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions
Renesas collaborated with Xilinx to design a version of the CLK-104 board to work with Xilinx's platform for
RFSoC solutions. The CLK-104 board uses an RF-PLL device to provide a reference for up to 12 RF clocks,
including one for an onboard RF-synthesizer device, and the 8V97003 as a reference clock to generate two
output clocks up to 18GHz for ADC/DAC applications. Two versions of the CLK-104 boards are available: the
CLK-104a uses an RF-PLL device with the 8V19N491-24, and the CLK-104b uses the 8V19N882. The rest of
the design is identical for both versions.
The CLK-104 is designed as a plug-in module to the Xilinx ZCU-1275 (16×16) platform. By plugging in to the
mainboard socket, the CLK-104 acquires power supplies, an I2C/SPI interface, and input reference clocks. The
following figure shows the bottom of the CLK-104 board with a male connector to match with ZCU-1275 board.
For information on how to operate and access the CLK-104 board, see the ZCU-1275 User Manual.
Figure 1. Back of CLK-104 Board with Mating Connector with Xilinx ZCU-1275
The CLK-104 board is designed to function as a standalone testing platform. For more information, see the
following sections.
Contents
1.
System Overview ........................................................................................................................................... 2
2.
Standalone Testing ........................................................................................................................................ 3
2.1
Power Supply ......................................................................................................................................... 3
3.
SPI Interface ................................................................................................................................................... 3
4.
Input Reference Selection ............................................................................................................................. 4
5.
Using Timing Commander to Program the Devices .................................................................................. 5
6.
Output Clock Monitoring/Measurement ...................................................................................................... 5
6.1
Example 1: Phase Noise Plot from J12/J13 (122.88MHz) .................................................................... 6
6.2
Example 2: Phase Noise Plot from 8V97003 #1 (1GHz) ....................................................................... 6
7.
Board Schematics ......................................................................................................................................... 7
8.
Revision History ............................................................................................................................................ 7
R31UH0011EU0100 Rev.1.00
Nov 26, 2021
Manual
Page 1
© 2021 Renesas Electronics
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Related Manuals for Renesas CLK-104a
Summary of Contents for Renesas CLK-104a
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Page 1: Table Of Contents
CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Renesas collaborated with Xilinx to design a version of the CLK-104 board to work with Xilinx’s platform for RFSoC solutions. The CLK-104 board uses an RF-PLL device to provide a reference for up to 12 RF clocks, including one for an onboard RF-synthesizer device, and the 8V97003 as a reference clock to generate two output clocks up to 18GHz for ADC/DAC applications. -
Page 2: System Overview
CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual 1. System Overview The CLK-104 board consists an RF-PLL device (8V19N491-24 or 8V19N882) and two RF-synthesizer devices (2x 8V97003). RF-PLL device can take one of the following three reference clocks as inputs to its CLK0/nCLK0 and CLK1/nCLK1 (both are differential inputs): ■... -
Page 3: Standalone Testing
CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual 2. Standalone Testing If a Xilinx ZCU-1275 board is not available, the CLK-104 board can be tested standalone. Please complete the following steps and information below to conduct a standalone test or evaluation. -
Page 4: Input Reference Selection
CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual 4. Input Reference Selection A 4-bit dip-switch (J11) is used to select one of three available reference clocks for the two input clocks of the RF-PLL (8V19N491-24 or 8V19N882). Two mux devices are used so the two input clocks going to the RF-PLL device can be selected individually. -
Page 5: Using Timing Commander To Program The Devices
CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual 5. Using Timing Commander to Program the Devices For ease of use, Renesas’ free-of-charge software tool – Timing Commander is recommended to configure and program the CLK-104 board/devices (8V19N491-24, 8V19N882, and 8V97003). If you have any questions on... -
Page 6: Example 1: Phase Noise Plot From J12/J13 (122.88Mhz)
CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual Example 1: Phase Noise Plot from J12/J13 (122.88MHz) Figure 7. Phase Noise Plot of 122.88MHz Output from 8V19N491-24 QREF_A2/nQREF_A2 Example 2: Phase Noise Plot from 8V97003 #1 (1GHz) Figure 8. Phase Noise Plot of 1000MHz Output from 8V97002 #1 ROUT_A/nROUT_A R31UH0011EU0100 Rev.1.00... -
Page 7: Board Schematics
CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual 7. Board Schematics The board schematics are located at the end of this document. 8. Revision History Revision Date Description 1.00 Nov 26, 2021 Initial release. R31UH0011EU0100 Rev.1.00 Page 7 Nov 26, 2021... - Page 17 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.