Hyperbus Interface; Table 8. Hyperbus Cs Truth Table; Table 9. Hyperbus Interface; Figure 5. Hyperbus Cs Scheme - STMicroelectronics SPC58NHADPT302S User Manual

6.2

Hyperbus interface

This paragraph describes the Hyperbus interface present on the mini module.
The SPC58NHADPT302S contains only one CS (CNS), whereas the memory device contains two CSs lines, one
for RAM and one for FLASH.
The second CS is emulated using one GPIO signal (PA[15]).
The following table shows the logic between CS/GPIO from SPC58NHADPT302S and CS0/CS1 from HyperRAM/
HyperFlash device
CSN
0
0
1
1
The following table describes all hardware HyperBus of the mini module, their position on PCB.
Symbol Description
U14 CMOS Inverter
IC1 TTL OR Gate
U13 RAM 256Mbit
UM2725 - Rev 1
Table 8. Hyperbus CS truth table
GPIO
0
1
0
1
Figure 5. Hyperbus CS scheme
Table 9. Hyperbus interface
Figure 9. Overview of SPC58NHADPT302S Rev. A mini module - Bottom
Figure 8. Overview of SPC58NHADPT302S Rev. A mini module - Top
Figure 8. Overview of SPC58NHADPT302S Rev. A mini module - Top
CS0
1
0
1
0
Position
UM2725
Hyperbus interface
CS1
0
1
1
1
- C1
- B1
- B2
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