Trigger Mode Selection Register - National Instruments VXI-MXI User Manual

Chapter 4

Trigger Mode Selection Register

VXIbus Address:
Attributes:
15 14
1 1
OMS2
OMS1
6
7
ECLSTAT1 ECLSTAT0
OTS3
OTS2
This register configures the ECL and TTL Trigger lines for interrupt generation and trigger
protocol generation. These bits are cleared on soft and hard resets.
Bit Mnemonic
15-8r, 1
5-4r,
2w
15-13w OMS[2-0]
© National Instruments Corporation
Base Address + 28 (hex)
Read/Write
13 12
1
1
OMS0 ITS3
5 4
1
1
OTS1
OTS0
Description
Reserved Bits
These bits are reserved and read back as ones. Write a zero when
writing to these bits.
Output Trigger Mode Select Bits
These bits select which trigger protocol or signal is driven on the
trigger line specified by the OTS[3-0] bits.
OMS2 OMS1 OMS0
0
0
0
0
1
1
1
11 10
1 1
ITS2 ITS1
3 2
TRIGOUT
TRIGIN
ETRIG 0
Trigger Output Mode
0 0 Disabled
0 1 Sync, Semi-Sync, or Async Source
1 0 Start-Stop Source
1 1 Semi-Sync Acceptor
0 0 Source from TRIG IN SMB
0 1 Reserved
1 X Reserved
4-41
Register Descriptions
9 8
R
1
1
ETOEN
ITS0
W
1 0
R
ASINT* SSINT*
ASIE SSIE
W
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