National Instruments VXI-MXI User Manual page 104

Register Descriptions
12r ACFAILINT
12w, 0
7w
11r BKOFF
11w BKOFFIE
10r TRIGINT
10w TRIGINTIE
9r SYSFAIL
9w SYSFAILIE
VXI-MXI User Manual
VXIbus ACFAIL Interrupt Status Bit
If this bit is set, an interrupt is currently driven on the VMEbus
interrupt line selected by the LINT[3-1] bits because the VXIbus
ACFAIL line became set. This bit is cleared on an interrupt
acknowledge cycle for the interrupt level selected by the LINT
[3-1] bits.
Reserved Bits
These bits are reserved. Write a zero when writing to these bits.
Backoff Status Bit
This bit is set if a VMEbus transfer to or from the MXIbus could
not complete because another MXIbus transfer to this module was
already in progress; in other words, a deadlock condition occurred.
The interrupt generated by this bit is cleared on an interrupt
acknowledge cycle for the interrupt level selected by the LINT
[3-1] bits. This bit is cleared by writing to the BOFFCLR bit in the
MXIbus Control Register.
Backoff Interrupt Enable Bit
If this bit is set, an interrupt is generated on the VMEbus interrupt
line selected by the LINT[3-1] bits when a VMEbus Backoff
condition occurs.
Trigger Interrupt Bit
This bit is set when either the ASINT* or SSINT* bit is cleared in
the Trigger Mode Selection Register. These bits become set and
generate an interrupt when the trigger signal selected by the
ITS[3-0] bits changes state. The interrupt generated by this bit is
cleared on an interrupt acknowledge cycle for the interrupt level
selected by the LINT[3-1] bits. This bit is cleared when the
ASACK and SSACK Registers are read.
Trigger Interrupt Enable Bit
If this bit is set, an interrupt is generated on the VMEbus interrupt
line selected by the LINT[3-1] bits when an ASINT* or SSINT*
interrupt occurs.
VXIbus SYSFAIL Status Bit
This bit reflects the status of the VXIbus SYSFAIL line.
VXIbus SYSFAIL Interrupt Enable Bit
If this bit is set, an interrupt is generated on the VMEbus interrupt
line selected by the LINT[3-1] bits when the VXIbus SYSFAIL
line is set.
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Chapter 4