National Instruments VXI-MXI User Manual page 98

Register Descriptions
1w DRVECL1
0w DRVECL0
VXI-MXI User Manual
Drive ECL Trigger Line 1 Bit
Setting this bit asserts the VXIbus ECL Trigger Line 1 after
synchronizing the signal with the 10 MHz clock.
Drive ECL Trigger Line 0
Setting this bit asserts the VXIbus ECL Trigger Line 0 after
synchronizing the signal with the 10 MHz clock.
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Chapter 4