Logical Address Window Register - National Instruments VXI-MXI User Manual

Register Descriptions

Logical Address Window Register

VXIbus Address:
Attributes:
This register defines the range of logical addresses that are mapped into and out of the VXI-MXI
through the MXIbus. This register defines a configuration window in the upper 16 KB of A16
space. These bits are cleared on a hard reset.
The CMODE bit in the MXIbus Control Register selects the format of this register. If the
CMODE bit is 0 (default), a Base/Size window comparison is used to determine the range of
addresses in the window. If the CMODE bit is set, an upper and lower bound is used to
determine the range of addresses in the window.
The Logical Address Window Register has the following format when the CMODE bit is
cleared:
15 14
0 LAEN
LAEN
0
7 6
LABASE7 LABASE6
Bit Mnemonic
15r/w 0
14r/w LAEN
13r/w LADIR
VXI-MXI User Manual
Base Address + A (hex)
Read/Write
13 12
LADIR 1
LADIR 0
5 4
LABASE5 LABASE4 LABASE3 LABASE2 LABASE1
Description
Reserved Bit
This bit is reserved and reads back as zero. Write a zero when
writing to these bits.
Logical Address Window Enable Bit
When this bit is set, the logical address mapping window is
enabled. When this bit is cleared, the logical address mapping
window is disabled except for the logical address of this device.
Access to the VXI-MXI's own configuration space is always
enabled.
Logical Address Window Direction Bit
When this bit is set, the logical address window applies to MXIbus
cycles that are mapped into VXIbus cycles (inward cycles). When
this bit is cleared, the logical address window applies to VXIbus
cycles that are mapped out into MXIbus cycles (outward cycles).
The complement of the defined range is mapped in the opposite
direction.
11 10
1 LASIZE2
0 LASIZE2
3 2
4-10 © National Instruments Corporation
Chapter 4
9 8
R
LASIZE1
LASIZE0
LASIZE1 LASIZE0
W
1
0
LABASE0
R/W