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Theory of Operation
Table 6-3. Transfer Responses for VMEbus Address Modifiers
AM5
AM4
AM3
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
Information specifying the number of bytes and which bytes are involved in a VMEbus transfer
is sent on data strobe lines DS1* and DS0*, address line A01, and the LWORD* line. During
MXIbus transfers, the same information is transferred on the Size line, and Address/Data lines 1
and 0 (AD01 and AD00). The VMEbus transfer size information is converted into MXIbus
transfer size information during a MXIbus master transfer. Table 6-4 compares this information
for the VMEbus and the MXIbus.
VXI-MXI User Manual
AM2
AM1
H
H
H
H
H
H
H
H
L
H
L
H
H
L
H
H
L
L
H
H
L
H
L
H
H
L
L
H
H
H
H
H
H
H
H
L
H
L
H
H
L
H
H
L
L
AM0
Transfer Type
H
A24 supervisory block transfer
L
A24 supervisory program access
H
A24 supervisory data access
H
A24 nonprivileged block transfer
L
A24 nonprivileged program access
H
A24 nonprivileged data access
H
A16 supervisory access
L
MXIbus transparent IACK cycle
H
A16 nonprivileged access
H
A32 supervisory block transfer
L
A32 supervisory program access
H
A32 supervisory data access
H
A32 nonprivileged block transfer
L
A32 nonprivileged program access
H
A32 nonprivileged data access
6-8
© National Instruments Corporation
Chapter 6
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