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Register Descriptions
MXIbus Lock Register
VXIbus Address:
Attributes:
15
14
1
1
0
0
6
7
1
1
0
0
The bit in this register performs differently depending on whether it was accessed by the
VMEbus or the MXIbus. This register is cleared on hard and soft resets.
Bit
Mnemonic
15-1r/w
1
0r/w
LOCKED
VXI-MXI User Manual
Base Address + 22 (hex)
Read/Write
13
12
1
1
0
0
5
4
1
1
0
0
Description
Reserved Bits
These bits are reserved and read back as ones. Write a zero when
writing to these bits.
Lock MXIbus or VXIbus Bit
When this bit is set by a VXIbus device, the MXIbus is locked by
that device as soon as the MXIbus is won by the VXI-MXI. When
the MXIbus is locked, indivisible operations to remote resources
can be performed across the MXIbus. When this bit is set by a
device from across the MXIbus, the VXIbus is locked by that
device so that indivisible operations to local VXIbus resources can
be performed from the MXIbus.
Similarly, when a VXIbus device reads this bit as a one, it
indicates that the MXIbus is locked. When a MXIbus device reads
this bit as a one, it indicates that the VXIbus is locked.
11
10
1
1
0
0
3
2
1
1
0
0
4-36
© National Instruments Corporation
Chapter 4
9
8
R
1
1
0
0
W
1
0
R
1
LOCKED
0
LOCKED
W
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