Mxibus Defined Registers; Mxibus Status/Control Register - National Instruments VXI-MXI User Manual

Chapter 4

MXIbus Defined Registers

MXIbus Status/Control Register

VXIbus Address:
Attributes:
15 14
RMWMODE CMODE
RMWMODE CMODE
6
7
MXISC
MXTRIGINT
MXTRIGEN
0
This register contains status and control bits for various types of MXIbus operators.
Bit Mnemonic
15r/w RMWMODE
© National Instruments Corporation
Base Address + 20 (hex)
Read/Write
13 12
1 1
ECL1EN ECL1DIR
5 4
MXSRSTINT MXACFAILINT
MXSRSTEN MXACFAILEN LNGMXSCTO
Description
Read/Modify Write Select Mode Bit
This bit, along with the MXIbus Address Modifiers, selects how
the VXI-MXI will treat a MXIbus cycle when the MXIbus Address
Strobe is held low for multiple data transfers. This bit is cleared on
hard and soft resets.
If the MXIbus address modifiers label the transfer for block mode,
the MXIbus block-mode transfer is converted to a VMEbus block-
mode transfer irrespective of the RMWMODE bit.
If this bit is cleared and the MXIbus address modifiers do not label
the transfer for block mode, the MXIbus cycle is interpreted as a
RMW (Read/Modify/Write) cycle, which is then converted into a
VMEbus RMW cycle.
If this bit is set and the MXIbus address modifiers do not label the
transfer for block mode, the MXIbus cycle is interpreted as a block
transfer and is converted into single transfer VMEbus accesses.
This mode should be used when transferring large amounts of data
with MXIbus block mode to a VMEbus device that does not
support block mode.
The following table summarizes the RMWMODE function.
11 10
MXSCTO INTLCK
ECL0EN ECL0DIR
3 2
LNGMXSCTO MXBERR
BOFFCLR
4-31
Register Descriptions
9 8
R
DSYSFAIL FAIR
DSYSFAIL DSYSRST
W
1 0
R
MXSYSFINT PARERR
0 0
W
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