Ml40X Control Register 2 - Xilinx ML40 Series User Manual

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ML40x Control Register 2

Table 2-5
Table 2-5: Control Register 2 (Address 0x9000000C)
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
shows Control Register 2 located at address 0x9000000C.
Bit(s)
0 (LSB) IIC SCL I/O Direction. Valid only when IIC GPIO is enabled (see
Register 2," Bit 6). Setting this bit to a 1 makes the GPIO IIC SCL bit a read input.
Setting this bit to 0 makes the GPIO IIC SCL bit a write output.
1 IIC SDA I/O Direction. Valid only when IIC GPIO is enabled (see
Register 2," Bit 6). Setting this bit to a 1 makes the GPIO IIC SDA bit a read input.
Setting this bit to 0 makes the GPIO IIC SDA bit a write output.
2 Error 1 LED Reset. Writing a 1 to this bit holds the Error 1 LED off. This bit must
be written back to a 0 to permit normal operation.
3 Error 1 LED Set. Writing a 1 to this bit holds the Error 1 LED on. This bit must be
written back to a 0 to permit normal operation.
4 Error 2 LED Reset. Writing a 1 to this bit holds the Error 2 LED off. This bit must
be written back to a 0 to permit normal operation. (ML401/ML402 only)
5 Error 2 LED Set. Writing a 1 to this bit holds the Error 2 LED on. This bit must be
written back to a 0 to permit normal operation. (ML401/ML402 only)
6 IIC GPIO. Writing this bit to a 1 makes the IIC SCL/SDA pins controlled via GPIO
registers. Writing this bit to a 0 makes IIC SCL/SDA pins controlled by the OPB
IIC Controller (if instantiated in system.mhs).
7 IIC PS/2. Writing this bit to a 1 makes the PS/2 mouse/keyboard pins controlled
via GPIO registers. Writing this bit to a 0 makes the PS/2 pins controlled by the
OPB Dual PS/2 Controller.
8 PS/2 Mouse Clock I/O Direction. Valid only when PS/2 GPIO is enabled (see
"ML40x Control Register 2,"
Clock bit a read input. Setting this bit to 0 makes the bit a write output.
9 PS/2 Mouse Data I/O Direction. Valid only when PS/2 GPIO is enabled (see
"ML40x Control Register
Data bit a read input. Setting this bit to 0 makes the bit a write output.
10 PS/2 Keyboard Clock I/O Direction. Valid only when PS/2 GPIO is enabled (see
"ML40x Control Register 2,"
Clock bit a read input. Setting this bit to 0 makes the bit a write output.
11 PS/2 Keyboard Data I/O Direction. Valid only when PS/2 GPIO is enabled (see
"ML40x Control Register 2,"
Data bit a read input. Setting this bit to 0 makes the bit a write output.
12 CPU Reset GPIO. Writing this bit to a 1 makes the state of the CPU Reset button
readable using ML40x Control Register 1, Bit 12. Setting this bit to a 1 prevents the
CPU Reset button from causing a system reset. This bit must be set back to 0 for
normal operation of the CPU Reset button.
13 USB Reset. Setting this bit to a 1 resets the USB controller chip. This bit must be set
back to 0 to permit normal operation of the USB controller.
31-14 (MSB) Reserved.
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ML40x Specific Registers
Description
Bit 7). Setting this bit to a 1 makes the PS/2 Mouse
2,", Bit 7). Setting this bit to a 1 makes the PS/2 Mouse
Bit 7). Setting this bit to a 1 makes the PS/2 Keyboard
Bit 7). Setting this bit to a 1 makes the PS/2 Keyboard
"ML40x Control
"ML40x Control
31