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Chapter 8: PLB TFT LCD Controller
Memory Map
Video Memory
The video memory is stored in a 2 MB region of memory consisting of 1024 data words
(1 word = 32 bits) per line by 512 lines per frame. Of this 1024 x 512 memory space, only the
first 640 columns and 480 rows are displayed on the screen.
For a given row (0 to 479) and column (0 to 639), the pixel color information is encoded as
shown in
Table 8-6: Pixel Color Encoding
78
Table
8-6.
Pixel Address
TFT Base Address +
(4096 * row) +
(4 * column)
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Bits
[31:24]
Undefined.
[23:18]
Red Pixel Data:
000000 = darkest → 111111 = brightest
[17:16]
Undefined.
[15:10]
Green Pixel Data:
000000 = darkest→111111 = brightest
[9:8]
Undefined.
[7:2]
Blue Pixel Data:
000000 = darkest→111111 = brightest
[1:0]
Undefined.
ML40x EDK Processor Reference Design
Description
UG082 (v5.0) June 30, 2006
R
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