Xilinx ML40 Series User Manual page 72

Chapter 8: PLB TFT LCD Controller
Table 8-2: PLB Master Signals
72
Name
PLB_MnAddrAck
PLB_MnBusy
PLB_MnErr
PLB_MnRdBTerm
PLB_MnRdDAck
PLB_MnRdDBus[0:63]
PLB_MnRdWdAddr[0:3]
PLB_MnRearbitrate
PLB_Mnssize[0:1]
PLB_MnWrBTerm
PLB_MnWrDAck
PLB_pendPri[0:1]
PLB_pendReq
PLB_reqPri[0:1]
Mn_abort
Mn_ABus[0:31]
Mn_BE[0:7]
Mn_busLock
Mn_compress
Mn_guarded
Mn_lockErr
Mn_msize[0:1]
Mn_ordered
Mn_priority[0:1]
Mn_rdBurst
Mn_request
Mn_RNW
Mn_size[0:3]
Mn_type[0:2]
Mn_wrBurst
Mn_wrDBus[0:63]
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Direction
Input PLB master address acknowledge
Input PLB master slave busy indicator
Input PLB master slave error indicator
Input PLB master terminate read burst indicator
Input PLB master read data acknowledge
Input PLB master read data bus
Input PLB master read word address
Input PLB master bus rearbitrate indicator
Input PLB slave data bus size
Input PLB master terminate write burst indicator
Input PLB master write data acknowledge
Input PLB pending request priority
Input PLB pending bus request indicator
Input PLB current request priority
Output Master abort bus request indicator
Output Master address bus
Output Master byte enables
Output Master bus lock
Output Master compressed data transfer indicator
Output Master guarded transfer indicator
Output Master lock error indicator
Output Master data bus size
Output Master synchronize transfer indicator
Output Master bus request priority
Output Master burst read transfer indicator
Output Master bus request
Output Master read/not write
Output Master transfer size
Output Master transfer type
Output Master burst write transfer indicator
Output Master write data bus
ML40x EDK Processor Reference Design
Description
UG082 (v5.0) June 30, 2006
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