Xilinx ML40 Series User Manual page 59

R
Table 6-5: Memory Map (Continued)
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Register Address Bits
Base Address + 12 [30]
[31]
Base Address + 16 [24:30]
[31]
Base Address + 20 [24:31]
Base Address + 24 [24:31]
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Read/
Write
W Clear/Reset Record FIFO:
0 = Do not Reset Record FIFO
1 = Reset Record FIFO. Resetting the record FIFO
also clears the "Record FIFO Overrun" status bit.
W Clear/Reset Play FIFO:
0 = Do not Reset Play FIFO
1 = Reset Play FIFO. Resetting the Play FIFO also
clears the "Play FIFO Underrun" status bit.
W AC97 Control Address Register:
Sets the 7-bit address of control or status register
in the Codec chip to be accessed. Writing to this
register clears the "Register Access Finish" status
bit.
W AC97 Control Address Register:
0 = Perform a write to the address specified
above. The write data comes from the "AC97
Control Data Write Register" which should be set
beforehand.
1 = Performs a read to the address above. Writing
to this register clears the "Register Access Finish"
status bit. This bit is asserted high when the
operation is complete.
R AC97 Status Data Read Register:
Returns data from the status register in the Codec
that was read by the command above. Data is
valid when the "Register Access Finish" flag is
set.
W AC97 Control Data Write Register:
Contains the data to be written to the control
register in the Codec. This register is used in
conjunction with the "AC97 Control Address
Register" described above.
Memory Map
Description
59