Xilinx ML40 Series User Manual page 66

Chapter 7: OPB PS/2 Controller (Dual)
Table 7-5: OPB PS/2 Slave Device Pin Description
Name Field Name
Base Address + 0 SRST
(Offset x00)
Base Address + 4 STR.6
(Offset x04) tx_full_sta
STR.7
rx_full_sta
Base Address + 8 RXR
(Offset x08)
Base Address + 12 TXR
(Offset x0c)
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Bit Direction
7 W Software Reset.
Writing '1' into this register results in the PS/2 controller
being reset to idle state. Also, registers at offset x04, x10, x14
will be reset by this bit as well.
6 R TX Register Full.
PS/2 Serial Interface Engine is busy. This register can only be
modified by PS/2 SIE hardware. Software does not have
direct write permission to change this field because this field
is set by the state machine in the SIE. Software can clear this
field indirectly is by using the SRST register.
7 R RX Register Full.
PS/2 Serial Interface Engine received a byte package. The
associated interrupt "rx_full" (INTSTA.3) will also be set.
Software does not have direct write permission to change
this field since this field is set by the state machine in the SIE.
Software can clear this field indirectly is by using the SRST
register.
[0:7] R RX received data.
[0:7] W TX transmission data.
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Description
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
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