Xilinx ML40 Series User Manual page 73

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Table 8-3: DCR Slave Signals
Table 8-4: External Output Pins
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Name
DCR_ABus[0:9]
DCR_DBusIn[0:31]
DCR_Read
DCR_Write
DCR_Ack
DCR_DBusOut[0:31]
Name
TFT_LCD_HSYNC
TFT_LCD_VSYNC
TFT_LCD_DE
TFT_LCD_CLK
TFT_LCD_DPS
TFT_LCD_R[5:0]
TFT_LCD_G[5:0]
TFT_LCD_B[5:0]
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Direction
Input DCR Address Bus
Input DCR Data Bus In
Input DCR Read Strobe
Input DCR Write Strobe
Output DCR Acknowledge
Output DCR Data Bus Out
Direction
Output Horizontal Sync (Negative Polarity)
Output Vertical Sync (Negative Polarity)
Output Data Enable
Output Video Clock
Output Selection of Scan Direction
Output Red Pixel Data
Output Green Pixel Data
Output Blue Pixel Data
Module Port Interface
Description
Description
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