Xilinx ML40 Series User Manual page 68

Chapter 7: OPB PS/2 Controller (Dual)
Table 7-5: OPB PS/2 Slave Device Pin Description (Continued)
Name Field Name
Base Address + 20 INTCLR.2
(Offset x14) rx_full
INTCLR.3
rx_err
INTCLR.4
rx_ovfl
INTCLR.5
tx_ack
INTCLR.6
tx_noak
INTCLR.7
wdt_toutl
* If software tries to read from INTCLR (offset x14), the value of INTSTA (offset x10) is returned.
Base Address + 24 INTMSET.2
(Offset x18) rx_full
INTMSET.3
rx_err
INTMSET.4
rx_ovf
INTMSET.5
tx_ack
INTMSET.6
tx_noack
INTMSET.7
wdt_tout
* If software tries to read from INTMSET (offset x18), the value of INTM register is returned.
68
Bit Direction
2 R*/W Interrupt Clear Register - RX data register full.
Writing a '1' to this field clears INTSTA.2.
Writing a '0' has no effect.
3 R*/W Interrupt Clear Register - RX data error.
Writing a '1' to this field clears INTSTA.3.
Writing a '0' has no effect.
4 R*/W Interrupt Clear Register - RX data register overflow.
Writing a '1' to this field clears INTSTA.4.
Writing a '0' has no effect.
5 R*/W Interrupt Clear Register - TX acknowledge received.
Writing a '1' to this field clears INTSTA.5.
Writing a '0' has no effect.
6 R*/W Interrupt Clear Register - TX acknowledge not received.
Writing a '1' to this field clears INTSTA.6.
Writing a '0' has no effect.
7 R*/W Interrupt Clear Register - Watch dog timer timeout.
Writing a '1' to this field clears INTSTA.7.
Writing a '0' has no effect.
2 R*/W Interrupt Mask Set Register - RX data register full. Writing a
'1' to this field sets INTM.2.
Writing a '0' has no effect.
3 R*/W Interrupt Mask Set Register - RX data error.
Writing a '1' to this field sets INTM.3.
Writing a '0' has no effect.
4 R*/W Interrupt Mask Set Register - RX data register overflow.
Writing a '1' to this field sets INTM.4.
Writing a '0' has no effect.
5 R*/W Interrupt Mask Set Register - TX acknowledge received.
Writing a '1' to this field sets INTM.5.
Writing a '0' has no effect.
6 R*/W Interrupt Mask Set Register - TX acknowledge not received.
Writing a '1' to this field sets INTM.6.
Writing a '0' has no effect.
7 R*/W Interrupt Mask Set Register - Watch dog timer timeout.
Writing a '1' to this field sets INTM.7.
Writing a '0' has no effect.
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Description
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
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