Register 2Dh (Offset = 2Dh) [Reset = 0H] - Texas Instruments AFE79 Series Programming & User Manual

JESD_SUBCHIP Register Map
Bit Field
RXD_SIG_INVALI
7-7
D_RD_OVR
RXD_SIG_INVALI
6-6
D_RD_VAL
RXC_SIG_INVALI
5-5
D_RD_OVR
RXC_SIG_INVALI
4-4
D_RD_VAL
RXB_SIG_INVALID
3-3
_RD_OVR
RXB_SIG_INVALID
2-2
_RD_VAL
RXA_SIG_INVALID
1-1
_RD_OVR
RXA_SIG_INVALID
0-0
_RD_VAL

2.3.11 Register 2Dh (offset = 2Dh) [reset = 0h]

7 6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
FBCD_SIG_INVALI
3-3
D_RD_OVR
FBCD_SIG_INVALI
2-2
D_RD_VAL
166
Serial Interface Register Maps
Table 2-54. Register 2C Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Figure 2-52. Register 2Dh
5 4
FBCD_SIG_IN
VALID_RD_OV
Table 2-55. Register 2D Field Descriptions
Type Reset
R/W 0h
R/W 0h
Copyright © 2020, Texas Instruments Incorporated
Description
FOR LOW POWER CONSUMPTION:
ASYNC FIFOs are gated based on sig-invalid from TDD
controller. Setting this register to 1 overrides this behaviour
and the gating of data depends on the value of
RXD_SIG_INVALID_RD_VAL.
FOR LOW POWER CONSUMPTION:
When RXD_SIG_INVALID_RD_OVR is 1,
setting this register to val = 0, gates the data
setting to val = 1, ungates the data
FOR LOW POWER CONSUMPTION:
ASYNC FIFOs are gated based on sig-invalid from TDD
controller. Setting this register to 1 overrides this behaviour
and the gating of data depends on the value of
RXC_SIG_INVALID_RD_VAL.
FOR LOW POWER CONSUMPTION:
When RXC_SIG_INVALID_RD_OVR is 1,
setting this register val = 0, gates the data
setting to val = 1, ungates the data
FOR LOW POWER CONSUMPTION:
ASYNC FIFOs are gated based on sig-invalid from TDD
controller. Setting this register to 1 overrides this behaviour
and the gating of data depends on the value of
RXB_SIG_INVALID_RD_VAL.
FOR LOW POWER CONSUMPTION:
When RXB_SIG_INVALID_RD_OVR is 1,
setting this register val = 0, gates the data
setting to val = 1, ungates the data
FOR LOW POWER CONSUMPTION:
ASYNC FIFOs are gated based on sig-invalid from TDD
controller. Setting this register to 1 overrides this behaviour
and the gating of data depends on the value of
RXC_SIG_INVALID_RD_VAL.
FOR LOW POWER CONSUMPTION:
When RXA_SIG_INVALID_RD_OVR is 1,
setting this register val = 0, gates the data
setting to val = 1, ungates the data
3 2
FBCD_SIG_IN
VALID_RD_VA
R L
R/W-0h R/W-0h
Description
FOR LOW POWER CONSUMPTION:
ASYNC FIFOs are gated based on sig-invalid from TDD
controller. Setting this register to 1 overrides this behaviour
and the gating of data depends on the value of
FBCD_SIG_INVALID_RD_VAL.
FOR LOW POWER CONSUMPTION:
When FBCD_SIG_INVALID_RD_OVR is 1,
setting this register val = 0, gates the data
setting to val = 1, ungates the data
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1 0
FBAB_SIG_INV FBAB_SIG_INV
ALID_RD_OVR ALID_RD_VAL
R/W-0h R/W-0h
SBAU337 – May 2020
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