Register 27H (Offset = 27H) [Reset = Ffh]; Register 29H (Offset = 29H) [Reset = 3H]; Register 2Ah (Offset = 2Ah) [Reset = 0H] - Texas Instruments AFE79 Series Programming & User Manual

JESD_SUBCHIP Register Map

2.3.6 Register 27h (offset = 27h) [reset = FFh]

7 6
SERDESCD_TXBCLK_ENA
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
SERDESCD_TXBC
7-4
LK_ENA
SERDESAB_TXBC
3-0
LK_ENA

2.3.7 Register 29h (offset = 29h) [reset = 3h]

7 6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
DUAL_2T2R1F_M
1-1
ODE_CD
DUAL_2T2R1F_M
0-0
ODE_AB

2.3.8 Register 2Ah (offset = 2Ah) [reset = 0h]

7 6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
164
Serial Interface Register Maps
Figure 2-47. Register 27h
5 4
R/W-Fh
Table 2-50. Register 27 Field Descriptions
Type
R/W
R/W
Figure 2-48. Register 29h
5 4
Table 2-51. Register 29 Field Descriptions
Type
R/W
R/W
Figure 2-49. Register 2Ah
5 4
Copyright © 2020, Texas Instruments Incorporated
3
SERDESAB_TXBCLK_ENA
Reset Description
register to enable SerdesCD STX5, STX6, STX7 and STX8
txbclks (0 -disable, 1 - enable)
[3] = STX8 txbclk enable
Fh
[2] = STX7 txbclk enable
[1] = STX6 txbclk enable
[0] = STX5 txbclk enable
register to enable SerdesAB STX1, STX2, STX3 and STX4
txbclks (0 -disable, 1 - enable)
[3] = STX4 txbclk enable
Fh
[2] = STX3 txbclk enable
[1] = STX2 txbclk enable
[0] = STX1 txbclk enable
3
Reset Description
Used for 2r1f_cd instance
Default mode is dual 2r1f modes.
For RX L1 and M16 cases (or) FB M4, make this bit 0.
1h
Recommended to use LATTE to configure this register as the
correct values and the sequence depends on the mode of
usage.
Used for 2r1f_ab instance
Default mode is dual 2r1f modes.
For RX L1 and M16 cases (or) FB M4, make this bit 0.
1h
Recommended to use LATTE to configure this register as the
correct values and the sequence depends on the mode of
usage.
3
DDC_RD_CLK
_FBCD_FBAB_
CLK_SYSREF_
MUX
R/W-0h
2 1
R/W-Fh
2 1
DUAL_2T2R1F DUAL_2T2R1F
_MODE_CD _MODE_AB
R/W-1h
2 1
DDC_RD_CLK DDC_RD_CLK
_RXD_RXB_CL _RXC_RXA_CL
K_SYSREF_M K_SYSREF_M
UX
R/W-0h
SBAU337 – May 2020
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0
0
R/W-1h
0
UX
R/W-0h