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ADC JESD Register Map
2.5.34 Register 48h (offset = 48h) [reset = 1h]
7
6
0
0
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
7-5
0
DDC_RD_CLK_RX
4-0
2_DIV_M
2.5.35 Register 49h (offset = 49h) [reset = 0h]
7
6
0
0
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
7-5
0
DDC_RD_CLK_RX
4-0
2_DIV_N_M1
2.5.36 Register 4Ah (offset = 4Ah) [reset = 1h]
7
6
0
0
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
7-5
0
DDC_RD_CLK_FB
4-0
_DIV_M
396
Serial Interface Register Maps
Figure 2-530. Register 48h
5
4
0
R/W-0h
Table 2-535. Register 48 Field Descriptions
Type
Reset
R/W
0h
R/W
1h
Figure 2-531. Register 49h
5
4
0
R/W-0h
Table 2-536. Register 49 Field Descriptions
Type
Reset
R/W
0h
R/W
0h
Figure 2-532. Register 4Ah
5
4
0
R/W-0h
Table 2-537. Register 4A Field Descriptions
Type
Reset
R/W
0h
R/W
1h
Copyright © 2020, Texas Instruments Incorporated
3
2
DDC_RD_CLK_RX2_DIV_M
R/W-1h
Description
Must read or write 0
M value of ddc divider.
Output of this divider, clock frequency should match the
RXB/RXD interface rate
3
2
DDC_RD_CLK_RX2_DIV_N_M1
R/W-0h
Description
Must read or write 0
N-1 value of ddc divider.
Output of this divider, clock frequency should match the
RXB/RXD interface rate
3
2
DDC_RD_CLK_FB_DIV_M
R/W-1h
Description
Must read or write 0
M value of ddc divider.
Output of this divider, clock frequency should match the
FBAB/FBCD interface rate
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1
0
1
0
1
0
SBAU337 – May 2020
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