Texas Instruments AFE79 Series Programming & User Manual page 394

ADC JESD Register Map
2.5.27 Register 41h (offset = 41h) [reset = 2h]
7 6
0 0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
7-5 0
RX1_ROOT_CLK_
4-0
DIV_N_M1
2.5.28 Register 42h (offset = 42h) [reset = 2h]
7 6
0 0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
7-5 0
RX2_ROOT_CLK_
4-0
DIV_M
2.5.29 Register 43h (offset = 43h) [reset = 2h]
7 6
0 0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
7-5 0
RX2_ROOT_CLK_
4-0
DIV_N_M1
2.5.30 Register 44h (offset = 44h) [reset = 2h]
7 6
0 0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
394
Serial Interface Register Maps
Figure 2-523. Register 41h
5 4
0
R/W-0h
Table 2-528. Register 41 Field Descriptions
Type Reset
R/W 0h
R/W 2h
Figure 2-524. Register 42h
5 4
0
R/W-0h
Table 2-529. Register 42 Field Descriptions
Type Reset
R/W 0h
R/W 2h
Figure 2-525. Register 43h
5 4
0
R/W-0h
Table 2-530. Register 43 Field Descriptions
Type Reset
R/W 0h
R/W 2h
Figure 2-526. Register 44h
5 4
0
R/W-0h
Copyright © 2020, Texas Instruments Incorporated
3 2
RX1_ROOT_CLK_DIV_N_M1
R/W-2h
Description
Must read or write 0
N value of root divider.
Output of this divider goes to ddc and jesd clock dividers
3 2
RX2_ROOT_CLK_DIV_M
R/W-2h
Description
Must read or write 0
M value of root divider.
Output of this divider goes to ddc and jesd clock dividers
3 2
RX2_ROOT_CLK_DIV_N_M1
R/W-2h
Description
Must read or write 0
N value of root divider.
Output of this divider goes to ddc and jesd clock dividers
3 2
FB_ROOT_CLK_DIV_M
R/W-2h
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1 0
1 0
1 0
1 0
SBAU337 – May 2020