Texas Instruments AFE79 Series Programming & User Manual page 185

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Bit Field
TXOCTETPATH7_
6-4
CLK_SEL
TXOCTETPATH6_
2-0
CLK_SEL
2.3.42 Register 50h (offset = 50h) [reset = 20h]
7 6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
RX_TX_LOOPBAC
5-5 K_FIFO_INIT_STA
TE
RX_TX_LOOPBAC
4-2
K_FIFO_OFFSET
RX_TX_LOOPBAC
1-1
K_MODE_TX1
RX_TX_LOOPBAC
0-0
K_MODE_TX0
2.3.43 Register 52h (offset = 52h) [reset = 0h]
7 6
TXB_B1_Q_DA TXB_B1_I_DAT
TA_NEGATION A_NEGATION
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
SBAU337 – May 2020
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Table 2-85. Register 4F Field Descriptions
Type Reset
R/W 7h
R/W 6h
Figure 2-83. Register 50h
5 4
RX_TX_LOOP RX_TX_LOOPBACK_FIFO_OFFSET
BACK_FIFO_IN
IT_STATE
R/W-1h
Table 2-86. Register 50 Field Descriptions
Type Reset
R/W 1h
R/W 0h
R/W 0h
R/W 0h
Figure 2-84. Register 52h
5 4
TXB_B0_Q_DA TXB_B0_I_DAT
TA_NEGATION A_NEGATION
R/W-0h R/W-0h
Copyright © 2020, Texas Instruments Incorporated
Description
Selects the input SERDES-Tx lane clk for data that is normally
supposed to be on STX8.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
Selects the input SERDES-Tx lane clk for data that is normally
supposed to be on STX7.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
3 2
R/W-0h
Description
Init state to release Async-FIFO between ADC_JESD and
DAC_JESD out of reset
0 : Reset State
1 : Func State
serdes loopback FIFO read delay i.e. FIFO offset
Enables loopback to between ADC_JESD and DAC_JESD for
lanes[5:8]
0 : No loopback
1 : Enable ADC_JESD lanes[5:8]
Enables loopback to between ADC_JESD and DAC_JESD for
lanes[1:4]
0 : No loopback
1 : Enable ADC_JESD lanes[1:4]
3 2
TXA_B1_Q_DA TXA_B1_I_DAT
TA_NEGATION A_NEGATION
R/W-0h R/W-0h
Serial Interface Register Maps
JESD_SUBCHIP Register Map
1 0
RX_TX_LOOP RX_TX_LOOP
BACK_MODE_ BACK_MODE_
TX1 TX0
R/W-0h R/W-0h
1 0
TXA_B0_Q_DA TXA_B0_I_DAT
TA_NEGATION A_NEGATION
R/W-0h R/W-0h
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