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2.4.152 Register C0h (offset = C0h) [reset = 0h]
7
6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
JESD_SHORTTES
7-0
T_INPUT4[7:0]
2.4.153 Register C1h (offset = C1h) [reset = 0h]
7
6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
JESD_SHORTTES
7-0
T_INPUT4[15:8]
2.4.154 Register C2h (offset = C2h) [reset = 0h]
7
6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
JESD_SHORTTES
7-0
T_INPUT5[7:0]
2.4.155 Register C3h (offset = C3h) [reset = 0h]
7
6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
SBAU337 – May 2020
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Figure 2-381. Register C0h
5
4
JESD_SHORTTEST_INPUT4[7:0]
R/W-0h
Table 2-385. Register C0 Field Descriptions
Type
Reset
R/W
0h
Figure 2-382. Register C1h
5
4
JESD_SHORTTEST_INPUT4[15:8]
R/W-0h
Table 2-386. Register C1 Field Descriptions
Type
Reset
R/W
0h
Figure 2-383. Register C2h
5
4
JESD_SHORTTEST_INPUT5[7:0]
R/W-0h
Table 2-387. Register C2 Field Descriptions
Type
Reset
R/W
0h
Figure 2-384. Register C3h
5
4
JESD_SHORTTEST_INPUT5[15:8]
R/W-0h
Copyright © 2020, Texas Instruments Incorporated
3
2
Description
short test pattern input
3
2
Description
short test pattern input
3
2
Description
short test pattern input
3
2
Serial Interface Register Maps
DAC JESD Register Map
1
0
1
0
1
0
1
0
319
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