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ld.h [%sp + imm6], %rs
Function
Signed halfword data transfer
Standard)
Extension 1) H[sp + imm19] ← rs(15:0)
Extension 2) H[sp + imm32] ← rs(15:0)
15
Code
0
1
0
|
|
IE
C
V
Flag
|
|
–
–
–
Mode
Src:Register direct %rs = %r0 to %r15
Dst:Register indirect with displacement
CLK
Two cycles
Description
(1) Standard
ld.h
The 16 low-order bits of the rs register are transferred to the specified memory location. The
content of the current SP with twice the 6-bit immediate imm6 added as displacement comprises
the memory address to be accessed. The least significant bit of the displacement is always 0.
(2) Extension 1
ext
ld.h
The ext instruction extends the displacement to a 19-bit quantity. As a result, the 16 low-
order bits of the rs register are transferred to the address indicated by the content of the SP with
the 19-bit immediate imm19 added. Make sure the imm6 specified here resides on a halfword
boundary (least significant bit = 0).
(3) Extension 2
ext
ext
ld.h
The two ext instructions extend the displacement to a 32-bit quantity. As a result, the 16 low-
order bits of the rs register are transferred to the address indicated by the content of the SP with
the 32-bit immediate imm32 added. Make sure the imm6 specified here resides on a halfword
boundary (least significant bit = 0).
Example
ext
0x1
ld.h
[%sp + 0x2],%r0
S1C33 FAMILY C33 PE CORE MANUAL
H[sp + imm6 × 2] ← rs(15:0)
12 11 10
9
|
|
1
1
0
imm6
|
|
|
|
|
Z
N
|
|
–
–
[%sp + imm6],%rs
imm13
[%sp + imm6],%rs
imm13
imm13
[%sp + imm6],%rs
; H[sp + 0x42] ← 16 low-order bits of r0
4
3
0
|
r s
|
|
|
|
|
; memory address = sp + imm6 × 2
; = imm19(18:6)
; memory address = sp + imm19,
; imm6 = imm19(5:0)
; = imm32(31:19)
; = imm32(18:6)
; memory address = sp + imm32,
; imm6 = imm32(5:0)
EPSON
7 DETAILS OF INSTRUCTIONS
0x58__
109
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