Table of Contents
Advertisement
7 DETAILS OF INSTRUCTIONS
sll %rd, imm5
Function
Logical shift to the left
Standard)
Extension 1) Unusable
Extension 2) Unusable
Code
When imm5(4) = 0, logical shift to the left by 0 to 15 bits
15
1
0
0
|
|
When imm5(4) = 1, logical shift to the left by 16 to 31 bits
15
0
0
1
|
|
IE
C
V
Flag
|
|
– ↔ ↔
–
–
Mode
Src:Immediate (unsigned)
Dst:Register direct %rd = %r0 to %r15
CLK
One cycle
Description
(1) Standard
The rd register is shifted as shown in the diagram below. The number of bits to be shifted can
be specified in the range of 0 to 31 by the 5-bit immediate imm5. Data "0" is placed in the least
significant bit of the rd register.
rd register
(after execution)
(2) Delayed instruction
This instruction may be executed as a delayed instruction by writing it directly after a branch
instruction with the "d" bit included.
156
Shift the content of rd to left as many bits as specified by imm5 (0 to 31), LSB ← 0
12 11
8
7
|
|
0
1
1
0
0
imm5(3:0)
|
|
|
|
|
12 11
8
7
|
|
0
0
1
1
1
imm5(3:0)
|
|
|
|
|
Z
N
|
|
31
4
3
0
|
r d
|
|
|
|
|
4
3
0
|
r d
|
|
|
|
|
EPSON
0x8C__
0x27__
0
0
0
S1C33 FAMILY C33 PE CORE MANUAL
Advertisement
Table of Contents
