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7 DETAILS OF INSTRUCTIONS
srl %rd, %rs
Function
Logical shift to the right
Standard)
Extension 1) Unusable
Extension 2) Unusable
15
Code
1
0
0
|
|
IE
C
V
Flag
|
|
– ↔ ↔
–
–
Mode
Src:Register direct %rs = %r0 to %r15
Dst:Register direct %rd = %r0 to %r15
CLK
One cycle
Description
(1) Standard
The rd register is shifted as shown in the diagram below. The number of bits to be shifted can be
specified in the range of 0 to 31 by the 5 low-order bits of the rs register. Data "0" is placed in
the most significant bit of the rd register.
(2) Delayed instruction
This instruction may be executed as a delayed instruction by writing it directly after a branch
instruction with the "d" bit included.
160
Shift the content of rd to right as many bits as specified by rs (0 to 31), MSB ← 0
12 11
8
7
|
|
0
1
0
0
1
|
|
|
|
|
Z
N
|
|
31
0
rd register
(after execution)
4
3
0
|
r s
r d
|
|
|
|
|
0
EPSON
0x89__
0
S1C33 FAMILY C33 PE CORE MANUAL
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