Principles Of Operation; System Module; Power Entry Module (Pem); Rear Transition Module (Rtm) - Viavi mA-1302 Operation Manual

Principles of Operation

Refer to
when reviewing content in this section.
The mA-1302 and mA-1305 AXIe Chassis are flexible development platforms that comply
to AXIe 1.0, Base Architecture Specification, Revision 3.0. The mA-1302 contains two
interchangeable instrument slots that accept AXIe modules; the mA-1305 contains five
interchangeable instrument slots.
The mA-1302/mA-1305 AXIe Chassis are comprised of several modules with specific
Chassis functionality as described in the following sections.

System Module

The Chassis System Module contains a System-on-Chip (SOC) that contains the
Intelligent Platform Management Interface (IPMI) Shelf Management Controller (ShMC)
which monitors and controls Chassis' functions. The System Module provides the PCIe
and Ethernet switch fabric interface necessary for instrument slot communication and
external user connectivity. The System Module also provides Slot Timing and Chassis
configuration and shelf management functions via the Web Browser User Interface (Web
UI).

Power Entry Module (PEM)

The PEM contains a programmable micro controller that manages the Chassis main power
supply and fan trays. The PEM monitors for ON/OFF, Wake-on-LAN and Wake-on-PCIe
power requests and is responsible for communicating power sequencing messages to the
Chassis Shelf Management Controller (ShMC). The PEM runs on standby power and
receives power continuously when the Chassis is connected to an AC Power Supply.

Rear Transition Module (RTM)

The RTM contains the Chassis Input/Output (I/O) connectors and reference clock. The I/O
Connector interfaces include Gigabit Ethernet (GbE), external PCIe, USB 3.0, WiFi, and
GPS antenna connections, programmable-threshold trigger I/O, and reference clock
I/O. The Chassis reference clock provides standard timing accuracy and can also be
disciplined by Global Navigation Satellite System (GNSS), IEEE-1588v2, Synchronous
Ethernet recovered clock, or external 10 MHz/100 MHz input.
Rev. D0
May 2020
Figure 1-3, mA-1302/mA-1305 AXIe Chassis Interconnect Diagram on page 1-5
mA-1302/mA-1305 AXIe Chassis Operation Manual
Chapter 1 mA-1302/mA-1305 Overview
Principles of Operation
Page 1-3