Intel ® Ich7R Low Pin Count (Lpc) Interface; Intel ® Ich7R Pci Interface; Table 2-5: Supported Hdd Specifications - IEI Technology PCIE-9450 User Manual

PCIE-9450 PICMG 1.3 CPU Card
Specification
IDE devices
PIO Mode
PIO Max Transfer Rate
DMA/UDMA designation
DMA/UDMA Max Transfer
Controller Interface

Table 2-5: Supported HDD Specifications

®
2.6.4 Intel ICH7R Low Pin Count (LPC) Interface
The ICH7R LPC interface complies with the LPC 1.1 specifications. The LPC bus from the
ICH7R is connected to the following components:
BIOS chipset
Super I/O chipset
®
2.6.5 Intel ICH7R PCI Interface
The PCI interface on the ICH7R is compliant with the PCI Revision 2.3 implementation.
Some of the features of the PCI interface are listed below.
PCI Revision 2.3 compliant
33MHz
5V tolerant PCI signals (except PME#)
Integrated PCI arbiter supports up to seven PCI bus masters
Three of the seven PCI bus masters are interfaces to the following onboard components:
PCI slot connector on the bottom of the CPU card
Broadcom PCI Express GbE interface
Winbond PCI-to-ISA bridge interface
Ultra ATA/100 Ultra ATA/66
2 2
0 – 4 0 – 4
16.6 MB/s 16.6 MB/s
UDMA 3 - 4 UDMA 3 – 4
100MB/s 66MB/s
5V 5V
Ultra ATA/33
2
0 – 4
16.6 MB/s
UDMA 2
33MB/s
5V
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