Omron SYSMAC C2000H Operation Manual page 94

Inputting, Modifying, and Checking the Program
TR 0
00000
Diagram B: Corrected Using a TR bit
TR 0
00000
This execution condition is then restored after executing the right-hand in-
struction by using the same TR bit as the operand of a LOAD instruction
00001
00002
In terms of actual instructions the above diagram would be as follows: The
status of IR 00000 is loaded (a LOAD instruction) to establish the initial ex-
ecution condition. This execution condition is then output using an OUTPUT
instruction to TR 0 to store the execution condition at the branching point.
The execution condition is then ANDed with the status of IR 00001 and in-
struction 1 is executed accordingly. The execution condition that was stored
at the branching point is then re-loaded (a LOAD instruction with TR 0 as the
operand), this is ANDed with the status of IR 00002, and instruction 2 is ex-
ecuted accordingly.
The following example shows an application using two TR bits.
TR 1
00001 00002
00003
00004
00005
In this example, TR 0 and TR 1 are used to store the execution conditions at
the branching points. After executing instruction 1, the execution condition
stored in TR 1 is loaded for an AND with the status IR 00003. The execution
condition stored in TR 0 is loaded twice, the first time for an AND with the
status of IR 00004 and the second time for an AND with the inverse of the
status of IR 00005.
TR bits can be used as many times as required as long as the same TR bit is
not used more than once in the same instruction block. Here, a new instruc-
tion block is begun each time execution returns to the bus bar. If, in a single
instruction block, it is necessary to have more than eight branching points
that require the execution condition be saved, interlocks (which are described
next) must be used.
When drawing a ladder diagram, be careful not to use TR bits unless neces-
sary. Often the number of instructions required for a program can be reduced
and ease of understanding a program increased by redrawing a diagram that
would otherwise required TR bits. In both of the following pairs of diagrams,
Address
00000
Instruction 1
00001
00002
Instruction 2
00003
00004
00005
00006
Address
00000
Instruction 1
00001
00002
Instruction 2
00003
00004
Instruction 3
00005
00006
Instruction 4
00007
00008
00009
00010
00011
00012
00013
00014
Section 4-6
Instruction Operands
LD
OUT TR
AND
Instruction 1
LD TR
AND
Instruction 2
Instruction Operands
LD 00000
OUT TR
AND 00001
OUT TR
AND 00002
OUT 00500
LD TR
AND 00003
OUT 00501
LD TR
AND 00004
OUT 00502
LD TR
AND NOT 00005
OUT 00503
00000
0
00001
0
00002
0
1
1
0
0
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