Page 1 Cat. No. W130-E1-05 SYSMAC Programmable Controllers C200H (CPU01-E/03-E/11-E) OPERATION MANUAL...
Page 2 C200H Programmable Controllers (CPU01-E/03-E/11-E) Operation Manual Revised June 2003...
Page 4 OMRON. No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is constantly striving to improve its high-quality products, the information contained in this manual is subject to change without notice.
Page 6: Table Of Contents
............OMRON Product Terminology .
Page 7 TABLE OF CONTENTS SECTION 5 Instruction Set ........Notation .
Page 8 TABLE OF CONTENTS Glossary ........Index .
Page 9 It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs. Descriptions of Peripheral Devices used with the C200H PCs and a table of other manuals available to use with this manual for special PC applica- tions are also provided.
Page 10 PRECAUTIONS This section provides general precautions for using the Programmable Controller (PC) and related devices. The information contained in this section is important for the safe and reliable application of the Programmable Con- troller. You must read this section and understand the information contained before attempting to set up or operate a PC system.
Page 11: Intended Audience
It is extremely important that a PC and all PC Units be used for the specified purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PC system to the above-mentioned applications.
Page 12: Operating Environment Precautions
Application Precautions • The PC outputs may remain ON or OFF due to deposition or burning of the output relays or destruction of the output transistors. As a countermeasure for such problems, external safety measures must be provided to ensure safety in the system.
Page 13 Application Precautions Caution Failure to abide by the following precautions could lead to faulty operation of the PC or the system, or could damage the PC or PC Units. Always heed these pre- cautions. • Fail-safe measures must be taken by the customer to ensure safety in the event of incorrect, missing, or abnormal signals caused by broken signal lines, momentary power interruptions, or other causes.
Page 14 Application Precautions • When replacing parts, be sure to confirm that the rating of a new part is correct. Not doing so may result in malfunction or burning. • Before touching a Unit, be sure to first touch a grounded metallic object in order to discharge any static built-up.
Page 15: Introduction
It also provides an overview of the process of programming and operating a PC and ex- plains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the C200H, and a table of other manuals available to use with this manual for special PC applications, are also provided.
Page 16: Overview
The problem is how to get the desired control signals from available inputs at appropriate times. To achieve proper control, the C200H uses a form of PC logic called ladder- diagram programming. This manual is written to explain ladder-diagram pro- gramming and to prepare the reader to program and operate the C200H.
Page 17: Pc Terminology
PC operation and are thus explained here. Because the C200H is a Rack PC, there is no one product that is a C200H PC. That is why we talk about the configuration of the PC, because a PC is a configuration of smaller Units.
Page 18: Omron Product Terminology
Appendix A Standard Models list products according to these groups. The term Unit is used to refer to all of the OMRON PC products. Al- though a Unit is any one of the building blocks that goes together to form a C200H PC, its meaning is generally, but not always, limited in context to refer to the Units that are mounted to a Rack.
Page 19: Peripheral Devices
PC program or to interface the PC to external devices to output the program or memory area data. Model numbers for all devices listed below are provided in Appendix A Standard Models. OMRON product names have been placed in bold when introduced in the following descrip-...
Page 20 Link Adapters.) Factory Intelligent Terminal: The FIT is an OMRON computer with specially designed software that allows you to perform all of the operations that are available with the GPC or LSS. Programs can also be output directly to an EPROM chip, floppy disk drive, or printing device without any additional interface.
Page 21: Available Manuals
Available Manuals Available Manuals The following table lists other manuals that may be required to program and/ or operate the C200H. Operation Manuals and/or Operation Guides are also provided with individual Units and are required for wiring and other specifica- tions.
Page 22: Lss Capabilities
Section 1-8 LSS Capabilities Name Cat. No. Contents Heat/Cool Temperature Control Unit Operation W240 Information on Heating and Cooling Temperature Manual Control Unit PID Control Unit Operation Manual W241 Information on PID Control Unit Cam Positioner Unit Operation Manual W224 Information on Cam Positioner Unit LSS Capabilities The LSS is a complete programming and control package designed for C-series...
Page 23 Section 1-8 LSS Capabilities Group Description DM (data memory) DM operations are used to edit DM data in hexadecimal or ASCII form. There are also features for copying, filling and printing DM data, as well as data disk save and retrieve operations. I/O TABLE I/O TABLE is used to edit, check, and print I/O tables.
Page 24 Section 1-8 LSS Capabilities 1-8-3 Offline and Online Operations Group Description SYSTEM SETUP The SYSTEM SETUP provides settings for the operating environment of the LSS, including the PC that’s being communicated with (including network and interface settings) and disk drive, comment, printer, PROM Writer, and monitor settings. It also provides settings for trans- fer of I/O table and data link tables to UM.
Page 25: Hardware Considerations
Hardware Considerations This section provides information on hardware aspects of the C200H that are relevant to programming and software op- eration. These include indicators on the CPU Unit and basic PC configuration. This information is covered in detail in the C200H Installation Guide.
Page 26: Indicators
I/O Units, and Link Units, which provide the physical I/O terminals corre- sponding to I/O points. A C200H CPU Rack can be used alone or it can be connected to other Racks to provide additional I/O points. The CPU Rack provides three, five, or eight slots to which these other Units can be mounted depending on the backplane used.
Page 27 With the CPU11-E CPU Unit, SYSMAC LINK and NET Link Units can be mounted to the two rightmost slots on the CPU Rack. Refer to the C200H Installation Guide for details about which slots can be used for which Units and other details about PC configuration. The way in which I/O points on Units are allocated in memory is described in 3-3 IR Area.
Page 28: Memory Areas
SECTION 3 Memory Areas Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is pro- vided with various memory areas for data, each of which performs a different function. The areas generally accessible by the user for use in programming are classified as data areas.
Page 29: Introduction
Section 3-2 Data Area Structure Introduction Details, including the name, acronym, range, and function of each area are summarized in the following table. All but the last three of these areas are data areas. Data and memory areas are normally referred to by their acro- nyms.
Page 30 Section 3-2 Data Area Structure and not entered, when programming. Any data area designation without an acronym is assumed to be in either the IR or SR area. Because IR and SR addresses run consecutively, the word or bit addresses are sufficient to differ- entiate these two areas.
Page 31: Ir (Internal Relay) Area
It is accessible both by bit and by word. In the C200H PC, the IR area is comprised of words 000 to 235. Words in the IR area that are used to control I/O points are called I/O words.
Page 32 Section 3-3 IR Area signed as I/O bits can be used as work bits. IR area work bits are reset when power is interrupted or PC operation is stopped. I/O Words If a Unit brings inputs into the PC, the bit assigned to it is an input bit; if the Unit sends an output from the PC, the bit is an output bit.
Page 33: Sr (Special Relay) Area
When using a C200H CPU Unit, do not set the unit number on a C500 Slave Rack to 4, be- cause there is no unit number 5. I/O words are allocated only to installed units, from left to right, and not to slots as in the C200H system.
Page 34 Section 3-4 SR Area turns one ON then OFF, the specified Link Unit will be restarted. Other con- trol bits are OFF until set by the user. Word(s) Bit(s) Function 00 to 07 Node loop status output area for operating level 0 of SYSMAC NET Link System 08 to 15 Node loop status output area for operating level 1 of...
Page 35: Remote I/O Systems
Section 3-4 SR Area Word(s) Bit(s) Function 00 to 07 FAL number output area. Low Battery Flag Cycle Time Error Flag I/O Verification Error Flag Host Computer to rack-mounting Host Link Unit Level 0 Error Flag Remote I/O Error Flag Normally ON Flag Normally OFF Flag First cycle...
Page 36: Link System Flags And Control Bits
Section 3-4 SR Area If the content of bits 12 through 15 is B, an error has occurred in a Remote I/O Master or Slave Unit, and the content of bits 08 through 11 will indicate the unit number, either 0 or 1, of the Master involved. In this case, bits 04 to 06 contain the unit number of the Slave Rack involved.
Page 37 Section 3-4 SR Area SYSMAC NET Link Loop SR 236 contains the SYSMAC NET Link Loop Status Flags. Bits 00 through Status Output 07 are the Loop Status Flags for operating level 0, and bits 08 through 15 are the Flags for operating level 1. The bit functions are shown below. Level 0: 07 06 05 04 03 02 01 00 Level 1: 15 14 13 12 11 10 09 08 Central Power Supply Unit:...
Page 38 Section 3-4 SR Area SYSMAC NET Link Systems Completion Name Meaning code Normal end Data transfer was completed successfully. Parameter error SEND(90)/RECV(98) instruction operands are not within specified ranges. Transmission impossible The System was reset during execution of the instruction or the destination node is not in the System.
Page 39 Section 3-4 SR Area tem in operating level 0; the other half, in a Subsystem in operating level 1. The actual bit assignments depend on whether the PC is in a Single-level PC Link System or a Multilevel PC Link System. Refer to the PC Link System Manual for details.
Page 40: Forced Status Hold Bit (Cpu11-E Only)
Section 3-4 SR Area Multilevel PC Link Systems Flag type Bit no. SR 247 SR 248 SR 249 SR 250 Run flags Unit #8, Unit #0, Unit #8, Unit #0, level 1 level 1 level 0 level 0 Unit #9, Unit #1, Unit #9, Unit #1,...
Page 41: I/O Status Hold Bit
Section 3-4 SR Area SR 25211 is not effective when switching to RUN mode. SR 25211 should be manipulated from a Peripheral Device, e.g., a Program- ming Console or FIT. Maintaining Status during The status of SR 25211 and thus the status of force-set/force-reset bits can Startup be maintained when power is turned off and on by inserting the Set System instruction (SYS(49)) in the program as step 00000 with the proper operand.
Page 42: Output Off Bit
Section 3-4 SR Area Operating without a Battery In the following cases, DM (DM 0000 to DM 0999), HR, AR, CNT, and SR area data will not be retained in the CPU Unit’s internal RAM when the power is turned OFF. •...
Page 43: Fal (Failure Alarm) Area
Section 3-4 SR Area 3-4-6 FAL (Failure Alarm) Area A 2-digit BCD FAL code is output to bits 25300 to 25307 when the FAL or FALS instruction is executed. These codes are user defined for use in error diagnosis, although the PC also outputs FAL codes to these bits, such as one caused by battery voltage drop.
Page 44: Step Flag
Section 3-4 SR Area Bit 25400 Bit 25401 1-min clock pulse 0.02-s clock pulse 30 s 30 s .01 s .01 s 1 min. .02 s Bit 25500 Bit 25501 0.1-s clock pulse 0.2-s clock pulse .05 s .05 s 0.1 s 0.1 s 0.1 s...
Page 45: Ar (Auxiliary Relay) Area
Section 3-5 AR Area AR (Auxiliary Relay) Area AR word addresses extend from AR 00 to AR 27; AR bit addresses extend from AR 0000 to AR 2715. Most AR area words and bits are dedicated to specific uses, such as transmission counters, flags, and control bits, and words AR 00 through AR 06 and AR 23 through AR 27 cannot be used for any other purpose.
Page 46: Optical Transmitting I/O Unit Error Flags
Section 3-5 AR Area Word(s) Bit(s) Function 12 to 15 00 to 15 Active Node Flags for SYSMAC LINK System nodes of operating level 1 00 to 15 SYSMAC LINK/SYSMAC NET Link System operating level 0 service time per cycle 00 to 15 SYSMAC LINK/SYSMAC NET Link System operating level 1 service time per cycle 18 to 21...
Page 47: Sysmac Link System Data Link Settings
Section 3-5 AR Area 3-5-2 SYSMAC LINK System Data Link Settings AR 0700 to AR 0703 and AR 0704 to AR 0707 are used to designate word allocations for operating levels 0 and 1 of the SYSMAC LINK System. Alloca- tion can be set to occur either according to settings from an FIT or automati- cally in the LR and/or DM areas.
Page 48: Sysmac Link/Sysmac Net Link System Service Time (Cpu11-E Only)
Section 3-5 AR Area Level 0 Level 1 Bit (body of table shows node numbers) AR 08 AR 12 AR 09 AR 13 AR 10 AR 14 AR 11 AR 15 *Communication Controller Error Flag **EEPROM Error Flag 3-5-5 SYSMAC LINK/SYSMAC NET Link System Service Time (CPU11-E only) AR 16 provides the time allocated to servicing operating level 0 of the SYS- MAC LINK System and/or SYSMAC NET Link System during each cycle...
Page 49: Terminal Mode Key Bits (Cpu11-E Only)
Section 3-5 AR Area 1, 2, 3... 1. Turn ON AR 2114 (Stop Bit). Set the desired date, day, and time, being careful not to turn OFF AR 2114 (Stop Bit) when setting the day of the week (they’re in the same word).
Page 50: Cpu Low Battery Flag (Cpu11-E Only)
Section 3-5 AR Area 3-5-9 CPU Low Battery Flag (CPU11-E Only) AR 2404 is the Battery Alarm Flag for the CPU11-E backup battery. AR 2404 is refreshed every cycle while the PC is in RUN or MONITOR mode. 3-5-10 SCAN(18) Cycle Time Flag (CPU11-E Only) AR 2405 turns ON when the cycle time set with SCAN(18) is shorter than the actual cycle time.
Page 51: Dm (Data Memory) Area
Section 3-6 DM Area DM (Data Memory) Area The DM area is divided into various parts as described in the following table. Addresses User Usage read/write DM 0000 to DM 0968 Read/write General User Area DM 0969 to DM 0999 Read/write Error History Area (CPU11-E only) DM 1000 to DM 1999...
Page 52 Section 3-6 DM Area Area Structure Error records occupy three words each stored between DM 0970 and DM 0999. The last record that was stored can be obtained via the content of DM 0969 (Error Record Pointer). The record number, DM words, and pointer val- ue for each of the ten records are as follows: Record Addresses...
Page 53: Hr (Holding Relay) Area
Section 3-8 TC Area to 0000, the Error History Area will be reset (i.e., cleared), and any further error codes will be recorded from the beginning of the Error History Area. AR 0715 (Error History Enable Bit) must be ON to reset the Error History Area. Special I/O Unit Data The DM area between 1000 and 1999 is allocated to Special I/O Units as shown below.
Page 54: Lr (Link Relay) Area
Section 3-9 LR Area Once defined, a TC number can be designated as an operand in one or more of certain set of instructions other than those listed above. When defined as a timer, a TC number designated as an operand takes a TIM prefix. The TIM prefix is used regardless of the timer instruction that was used to define the timer.
Page 55: Program Memory
Section 3-11 TR Area 3-10 Program Memory Program Memory is where the user program is stored. The amount of Pro- gram Memory available is either 4K or 8K words, depending on the type of Memory Unit mounted to the CPU. Memory Units come in different types, such as RAM and ROM Units, and for each type there are different sizes.
Page 56: Writing And Inputting The Program
SECTION 4 Writing and Inputting the Program This section explains the basic steps and concepts involved in writing a basic ladder diagram program, inputting the pro- gram into memory, and executing it. It introduces the instructions that are used to build the basic structure of the ladder diagram and control its execution.
Page 57: Basic Procedure
Section 4-2 Instruction Terminology Basic Procedure There are several basic steps involved in writing a program. Sheets that can be copied to aid in programming are provided in Appendix F Word Assign- ment Recording Sheets and Appendix G Program Coding Sheet. 1, 2, 3...
Page 58: Basic Ladder Diagrams
Section 4-3 Basic Ladder Diagrams designated as an operand is called an operand word. If the actual value is entered as a constant, it is preceded by # to indicate that it is not an address. Other terms used in describing instructions are introduced in Section 5 In- struction Set.
Page 59: Mnemonic Code
Section 4-3 Basic Ladder Diagrams something to happen when a bit is ON, and a normally closed condition when you want something to happen when a bit is OFF. 00000 Instruction is executed Instruction when IR bit 00000 is ON. Normally open condition 00000...
Page 60: Ladder Instructions
Section 4-3 Basic Ladder Diagrams structions require no operands, while others require up to three operands, Program Memory addresses can be from one to four words long. Program Memory addresses start at 00000 and run until the capacity of Pro- gram Memory has been exhausted.
Page 61 Section 4-3 Basic Ladder Diagrams quires one line of mnemonic code. “Instruction” is used as a dummy instruc- tion in the following examples and could be any of the right-hand instructions described later in this manual. 00000 Address Instruction Operands A LOAD instruction.
Page 62 Section 4-3 Basic Ladder Diagrams (in order from the top) to a LOAD NOT, an OR NOT, and an OR instruction. Again, each of these instructions requires one line of mnemonic code. 00000 Instruction 00100 LR 0000 Address Instruction Operands 00000 00000 00001...
Page 63: Output And Output Not
Section 4-3 Basic Ladder Diagrams tion, and that’s where AND LOAD and OR LOAD instructions are used. Be- fore we consider more complicated diagrams, however, we’ll look at the in- structions required to complete a simple “input-output” program. 4-3-4 OUTPUT and OUTPUT NOT The simplest way to output the results of combining execution conditions is to output it directly with the OUTPUT and OUTPUT NOT.
Page 64: Logic Block Instructions
Section 4-3 Basic Ladder Diagrams described later. The END instruction requires no operands and no conditions can be placed on the same instruction line with it. 00000 00001 Instruction Program execution END(01) ends here. Address Instruction Operands 00000 00000 00001 AND NOT 00001 00002...
Page 65 Section 4-3 Basic Ladder Diagrams OR NOT between just IR 00003 and the result of an AND between IR 00002 and the first OR. What we need is a way to do the OR (NOT)’s independently and then combine the results. To do this, we can use the LOAD or LOAD NOT instruction in the middle of an instruction line.
Page 66 Section 4-3 Basic Ladder Diagrams blocks to be combined, starting each block with LOAD or LOAD NOT, and then to code the logic block instructions which combine them. In this case, the instructions for the last pair of blocks should be combined first, and then each preceding block should be combined, working progressively back to the first block.
Page 67 Section 4-3 Basic Ladder Diagrams or the three blocks can be coded first followed by two OR LOADs. The mne- monic codes for both methods are shown below. Address Instruction Operands Address Instruction Operands 00000 00000 00000 00000 00001 AND NOT 00001 00001 AND NOT...
Page 68 Section 4-3 Basic Ladder Diagrams lowed by the one to combine the execution condition resulting from the first logic block instruction and the execution condition of the logic block third from the end, and on back to the first logic block that is being combined. Block Address Instruction Operands...
Page 69 Section 4-3 Basic Ladder Diagrams blocks a and b would be combined using AND LOAD as shown above, and then block c would be coded and a second AND LOAD would be used to combined it with the execution condition from the first AND LOAD. Then block d would be coded, a third AND LOAD would be used to combine the execution condition from block d with the execution condition from the sec- ond AND LOAD, and so on through to block n.
Page 70 Section 4-3 Basic Ladder Diagrams last two blocks and working backward. The OR LOAD at program address 00008 combines blocks blocks d and e, the following AND LOAD combines the resulting execution condition with that of block c, etc. Address Instruction Operands 00000 00001...
Page 71: The Programming Console
Section 4-4 The Programming Console tion condition of block c with the execution condition resulting from the nor- mally closed condition assigned IR 00003. The rest of the diagram can be coded with OR, AND, and AND NOT instructions. The logical flow for this and the resulting code are shown below.
Page 72: The Keyboard
Section 4-4 The Programming Console gramming Console and the operation necessary to prepare for program in- put. 4-6 Inputting, Modifying, and Checking the Program describes actual procedures for inputting the program into memory. Depending on the model of Programming Console used, it is either con- nected to the CPU via a Programming Console Adapter and Connecting Ca- ble or it is mounted directly to the CPU.
Page 73: Pc Modes
Section 4-4 The Programming Console The gray keys other than the SHIFT key have either the mnemonic name of the instruction or the abbreviation of the data area written on them. The func- tions of these keys are described below. Pressed before the function code when inputting an instruction via its function code.
Page 74 Section 4-4 The Programming Console operation as well as the procedures that are possible from the Programming Console. RUN mode is the mode used for normal program execution. When the switch is set to RUN and the START input on the CPU Power Supply Unit is ON, the CPU will begin executing the program according to the program written in its Program Memory.
Page 75: Preparation For Operation
Section 4-5 Preparation for Operation The mode will not change when a peripheral device is removed from the PC after PC power is turned on. DANGER! Always confirm that the Programming Console is in PROGRAM mode when turning on the PC with a Programming Console connected unless another mode is desired for a specific purpose.
Page 76: Buzzer
Section 4-5 Preparation for Operation The PC prompts you for a password when PC power is turned on or, if PC power is already on, after the Programming Console has been connected to the PC. To gain access to the system when the “Password!” message ap- pears, press CLR and then MONTR.
Page 77 Section 4-5 Preparation for Operation Key Sequence Program Memory cleared from designated address. Both AR and HR areas TC area Retained if pressed DM area The following procedure is used to clear memory completely. All Clear Continue pressing the CLR key once for each error message until “00000”...
Page 78: Registering The I/O Table
I/O table remains in memory, a new I/O table must also be registered when- ever I/O Units are changed. Unlike the C500H and C1000H PCs, C200H memory is allocated to slots in the CPU and Extension I/O Racks, so it is not necessary to register the I/O table.
Page 79: Clearing Error Messages
Section 4-5 Preparation for Operation Initial I/O Table Registration Memory cleared completely Register I/O table 4-5-5 Clearing Error Messages After the I/O table has been registered, any error messages recorded in memory should be cleared. It is assumed here that the causes of any of the errors for which error messages appear have already been taken care of.
Page 80: Reading The I/O Table
Section 4-5 Preparation for Operation Example (No errors) (An error occurred) Actual I/O words Registered I/O table words I/O slot number Rack number Meaning of Displays Duplication Indicates a Remote I/O Unit that has not been registered 4-5-7 Reading the I/O Table The I/O Table Read operation is used to access the I/O table that is currently registered in the CPU memory.
Page 81 I/O Unit Designations for Displays (see I/O Units Mounted in Remote Slave Racks, next page) C500, 1000H/C2000H I/O Units No. of points Input Unit Output Unit C200H I/O Units No. of points Input Unit Output Unit Note: (*) is i for non-fatal errors or F_...
Page 82: Clearing The I/O Table
Section 4-5 Preparation for Operation I/O Units I/O word number I/O type: i: (input), o: (output) Unit number (0 to 9) Rack number (0 to 2) Special I/O Units Blank: Unit 1 exclusively Unit 2 exclusively C: High-speed Counter Special I/O N: Host Link Unit Unit type: A: Other...
Page 83: Net Link Table Transfer
Section 4-5 Preparation for Operation tion based on the I/O Units mounted when the I/O Table Clear operation is performed. The I/O Table Clear operation will reset all Special I/O Units and Link Units mounted at the time. Do not perform the I/O Table Clear operation when a Host or PC Link Unit, Remote I/O Master Unit, High-speed Counter Unit, Po- sition Control Unit, or other Special I/O Unit is in operation.
Page 84 Section 4-5 Preparation for Operation Key Sequence Example The following indicates that the I/O table cannot be transferred.
Page 85: Inputting, Modifying, And Checking The Program
Section 4-6 Inputting, Modifying, and Checking the Program Inputting, Modifying, and Checking the Program Once a program is written in mnemonic code, it can be input directly into the PC from a Programming Console. Mnemonic code is keyed into Program Memory addresses from the Programming Console.
Page 86: Entering And Editing Programs
Section 4-6 Inputting, Modifying, and Checking the Program Example If the following mnemonic code has already been input into Program Memory, the key inputs below would produce the displays shown. Address Instruction Operands 00200 00000 00201 00001 00202 0123 00203 00100 4-6-2 Entering and Editing Programs...
Page 87 Section 4-6 Inputting, Modifying, and Checking the Program Inputting SV for Counters The SV (set value) for a timer or counter is generally entered as a constant, and Timers although inputting the address of a word that holds the SV is also possible. When inputting an SV as a constant, CONT/# is not required;...
Page 88 Section 4-6 Inputting, Modifying, and Checking the Program Example The following program can be entered using the key inputs shown below. Displays will appear as indicated. Address Instruction Operands 00200 00002 00201 0123 00202 TIMH(15) 0500 Error Messages The following error messages may appear when inputting a program. Correct the error as indicated and continue with the input operation.
Page 89: Checking The Program
Section 4-6 Inputting, Modifying, and Checking the Program the displays shown below will be replaced with numeric data, normally an address, in the actual display. Message Cause and correction An attempt was made to write to ROM, or to write-protected RAM or EEPROM. Ensure that a RAM or EEPROM Unit is mounted and that its write-protect switch is set to OFF.
Page 90 Section 4-6 Inputting, Modifying, and Checking the Program Many of the following errors are for instructions that have not yet been de- scribed yet. Refer to 4-7 Controlling Bit Status or to Section 5 Instruction Set for details on these. Type Message Meaning and appropriate response...
Page 91: Displaying The Cycle Time
Section 4-6 Inputting, Modifying, and Checking the Program Example The following example shows some of the displays that can appear as a re- sult of a program check. Display #1 Halts program check Display #2 Check continues until END(01) Display #3 When errors are found 4-6-4 Displaying the Cycle Time...
Page 92: Program Searches
Section 4-6 Inputting, Modifying, and Checking the Program Example 4-6-5 Program Searches The program can be searched for occurrences of any designated instruction or data area address used in an instruction. Searches can be performed from any currently displayed address or from a cleared display. To designate a bit address, press SHIFT, press CONT/#, then input the ad- dress, including any data area designation required, and press SRCH.
Page 93: Inserting And Deleting Instructions
Section 4-6 Inputting, Modifying, and Checking the Program Example: Instruction Search Example: Bit Search 4-6-6 Inserting and Deleting Instructions In PROGRAM mode, any instruction that is currently displayed can be de- leted or another instruction can be inserted before it. These are not possible in RUN or MONITOR modes.
Page 94 Section 4-6 Inputting, Modifying, and Checking the Program words are required for the instruction, input these in the same way as when inputting the program initially. To delete an instruction, display the instruction word of the instruction to be deleted and then press DEL and the up key. All the words for the designated instruction will be deleted.
Page 95 Section 4-6 Inputting, Modifying, and Checking the Program Inserting an Instruction Find the address prior to the inser- tion point Program After Insertion Address Instruction Operands 00000 00100 00001 00101 00002 00201 00003 AND NOT 00102 00004 OR LD 00005 00103 00006 00105...
Page 96: Branching Instruction Lines
Section 4-6 Inputting, Modifying, and Checking the Program 4-6-7 Branching Instruction Lines When an instruction line branches into two or more lines, it is sometimes necessary to use either interlocks or TR bits to maintain the execution condi- tion that existed at a branching point. This is because instruction lines are executed across to a right-hand instruction before returning to the branching point to execute instructions on a branch line.
Page 97 Section 4-6 Inputting, Modifying, and Checking the Program This execution condition is then restored after executing the right-hand in- struction by using the same TR bit as the operand of a LOAD instruction TR 0 Address Instruction Operands 00000 00001 00000 00000 Instruction 1...
Page 98 Section 4-6 Inputting, Modifying, and Checking the Program and ease of understanding a program increased by redrawing a diagram that would otherwise required TR bits. In both of the following pairs of diagrams, the bottom versions require fewer instructions and do not require TR bits. In the first example, this is achieved by reorganizing the parts of the instruction block: the bottom one, by separating the second OUTPUT instruction and using another LOAD instruction to create the proper execution condition for...
Page 99 Section 4-6 Inputting, Modifying, and Checking the Program (ILC(03)) instructions to eliminate the branching point completely while allow- ing a specific execution condition to control a group of instructions. The IN- TERLOCK and INTERLOCK CLEAR instructions are always used together. When an INTERLOCK instruction is placed before a section of a ladder pro- gram, the execution condition for the INTERLOCK instruction will control the execution of all instruction up to the next INTERLOCK CLEAR instruction.
Page 100: Jumps
Section 4-6 Inputting, Modifying, and Checking the Program As shown in the following diagram, more than one INTERLOCK instruction can be used within one instruction block; each is effective through the next INTERLOCK CLEAR instruction. 00000 IL(02) Address Instruction Operands 00000 00000 00001...
Page 101 Section 4-6 Inputting, Modifying, and Checking the Program did not exist. Diagram B from the TR bit and interlock example could be re- drawn as shown below using a jump. Although 01 has been used as the jump number, any number between 01 and 99 could be used as long as it has not already been used in a different part of the program.
Page 102: Controlling Bit Status
Section 4-7 Controlling Bit Status Controlling Bit Status There are five instructions that can be used generally to control individual bit status. These are the OUTPUT, OUTPUT NOT, DIFFERENTIATE UP, DIFFERENTIATE DOWN, and KEEP instructions. All of these instructions appear as the last instruction in an instruction line and take a bit address for an operand.
Page 103: Work Bits (Internal Relays)
Section 4-8 Work Bits one instruction line, the instruction lines are coded first before the instruction that they control. Address Instruction Operands 00002 00003 00000 00002 S: set input KEEP(11) 00001 AND NOT 00003 HR 0000 00002 00004 00004 00003 00005 R: reset input 00004...
Page 104 Section 4-8 Work Bits Work Bit Applications Examples given later in this subsection show two of the most common ways to employ work bits. These should act as a guide to the almost limitless num- ber of ways in which the work bits can be used. Whenever difficulties arise in programming a control action, consideration should be given to work bits and how they might be used to simplify programming.
Page 105: Programming Precautions
Section 4-9 Programming Precautions ple, IR 00100 must be left ON continuously as long as IR 00001 is ON and both IR 00002 and IR 00003 are OFF, or as long as IR 00004 is ON and IR 00005 is OFF. It must be turned ON for only one cycle each time IR 00000 turns ON (unless one of the preceding conditions is keeping it ON continu- ously).
Page 106 Section 4-9 Programming Precautions The number of times any particular bit can be assigned to conditions is not limited, so use them as many times as required to simplify your program. Often, complicated programs are the result of attempts to reduce the number of times a bit is used.
Page 107: Program Execution
Section 4-10 Program Execution 4-10 Program Execution When program execution is started, the CPU cycles the program from top to bottom, checking all conditions and executing all instructions accordingly as it moves down the bus bar. It is important that instructions be placed in the proper order so that, for example, the desired data is moved to a word before that word is used as the operand for an instruction.
Page 108 SECTION 5 Instruction Set The C200H PC has a large programming instruction set that allows for easy programming of complicated control proc- esses. This section explains each instruction individually and provides the ladder diagram symbol, data areas, and flags used with each.
Page 109 5-16 Data Conversion ................5-16-1 BCD-TO-BINARY –...
Page 110: Notation
Section 5-3 Data Areas, Definer Values, and Flags Notation In the remainder of this manual, all instructions will be referred to by their mnemonics. For example, the Output instruction will be called OUT; the AND Load instruction, AND LD. If you’re not sure of the instruction a mnemonic is used for, refer to Appendix B Programming Instructions.
Page 111 Section 5-3 Data Areas, Definer Values, and Flags will have access to the other area. The border between the IR and SR areas can, however, be crossed for a single operand, i.e., the last bit in the IR area may be specified for an operand that requires more than one word as long as the SR area is also allowed for that operand.
Page 112: Differentiated Instructions
Refer to 5-8 INTERLOCK and INTERLOCK CLEAR – IL(02) and IL(03) for the effects of interlocks on differentiated instructions. The C200H also provides differentiation instructions: DIFU(13) and DIFD(14). DIFU(13) operates the same as a differentiated instruction, but is used to turn ON a bit for one cycle.
Page 113: Coding Right-Hand Instructions
Section 5-5 Coding Right-hand Instructions Coding Right-hand Instructions Writing mnemonic code for ladder instructions is described in Section 4 Writ- ing and Inputting the Program. Converting the information in the ladder dia- gram symbol for all other instructions follows the same pattern, as described below, and is not specified for each instruction individually.
Page 114 Section 5-5 Coding Right-hand Instructions The following diagram and corresponding mnemonic code illustrates the points described above. Address Instruction Data 00000 00001 00000 00000 DIFU(13) 22500 00002 00001 00001 00002 00002 00003 DIFU(13) 22500 00100 00200 22500 BCNT(67) 00004 00100 01001 01002 LR 6300 #0001...
Page 115: Ladder Diagram Instructions
Section 5-6 Ladder Diagram Instructions LD or LD NOT, to form ‘logic blocks’ that are combined by the right-hand in- struction. An example of this for SFT(10) is shown below. Address Instruction Data 00000 00001 00000 00000 SFT(10) 00002 00001 00001 HR 00 00002...
Page 116: And Load And Or Load
Section 5-6 Ladder Diagram Instructions B: Bit OR – OR IR, SR, AR, HR, TC, LR B: Bit OR NOT – OR NOT IR, SR, AR, HR, TC, LR Limitations There is no limit to the number of any of these instructions, or restrictions in the order in which they must be used, as long as the memory capacity of the PC is not exceeded.
Page 117: Bit Control Instructions
Section 5-7 Bit Control Instructions In order to draw ladder diagrams, it is not necessary to use AND LD and OR LD instructions, nor are they necessary when inputting ladder diagrams di- rectly, as is possible from the GPC. They are required, however, to convert the program to and input it in mnemonic form.
Page 118: Differentiate Up And Down - Difu(13) And Difd(14)
Section 5-7 Bit Control Instructions Flags There are no flags affected by these instructions. 5-7-2 DIFFERENTIATE UP and DOWN – DIFU(13) and DIFD(14) Ladder Symbols Operand Data Areas B: Bit DIFU(13) B IR, AR, HR, LR B: Bit DIFD(14) B IR, AR, HR, LR Limitations Any output bit can generally be used in only one instruction that controls its...
Page 119: Keep - Keep(11)
Section 5-7 Bit Control Instructions ample of how DIFU(13) can be used to ensure that CMP(20) is executed only once each time the desired execution condition goes ON. 00000 Address Instruction Operands CMP(20) 00000 00000 HR 10 00001 CMP(20) Diagram A DM 0000 0000 00000...
Page 120 Section 5-7 Bit Control Instructions the set input; R, the reset input. KEEP(11) operates like a latching relay that is set by S and reset by R. When S turns ON, the designated bit will go ON and stay ON until reset, re- gardless of whether S stays ON or goes OFF.
Page 121: Interlock And Interlock Clear - Il(02) And Ilc(03)
Section 5-8 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) Example If a HR bit or an AR bit is used, bit status will be retained even during a power interruption. KEEP(11) can thus be used to program bits that will main- tain status after restarting the PC following a power interruption.
Page 122 Section 5-8 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be used several times in a row, with each IL(02) creating an interlocked section through the next ILC(03). ILC(03) cannot be used unless there is at least one IL(02) between it and any previous ILC(03).
Page 123: Jump And Jump End - Jmp(04) And Jme(05)
Section 5-9 JUMP and JUMP END – JMP(04) and JME(05) Example The following diagram shows IL(02) being used twice with one ILC(03). Address Instruction Operands 00000 IL(02) 00000 00000 00001 00001 IL(02) TIM 511 TIM 511 00002 00001 #0015 001.5 s 00003 00002 0015...
Page 124: End - End(01)
Section 5-10 END – END(01) any instructions in between. The status of timers, counters, bits used in OUT, bits used in OUT NOT, and all other status bits controlled by the instructions between JMP(04) and JMP(05) will not be changed. Each of these jump numbers can be used to define only one jump.
Page 125: No Operation - Nop(00)
Section 5-12 Timer and Counter Instructions 5-11 NO OPERATION – NOP(00) Description NOP(00) is not generally required in programming and there is no ladder symbol for it. When NOP(00) is found in a program, nothing is executed and the program execution moves to the next instruction. When memory is cleared prior to programming, NOP(00) is written at all addresses.
Page 126: Timer - Tim
Section 5-12 Timer and Counter Instructions 5-12-1 TIMER – TIM Definer Values N: TC number Ladder Symbol # (000 through 511) TIM N Operand Data Areas SV: Set value (word, BCD) IR, AR, DM, HR, LR, # Limitations SV is between 000.0 and 999.9. The decimal point is not entered. The SV of the timers can be set in the range #0000 to #9999 (BCD).
Page 127 Section 5-12 Timer and Counter Instructions Flags SV is not in BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) Examples All of the following examples use OUT in diagrams that would generally be used to control output bits in the IR area.
Page 128 Section 5-12 Timer and Counter Instructions To create delays, the Completion Flags for two TIM are used to determine the execution conditions for setting and reset the bit designated for KEEP(11). The bit whose manipulation is to be delayed is used in KEEP(11). Turning ON and OFF the bit designated for KEEP(11) is thus delayed by the SV for the two TIM.
Page 129 Section 5-12 Timer and Counter Instructions 01000 TIM 001 Address Instruction Operands 01000 00000 01000 00001 AND NOT 00000 00002 00000 00003 01000 01000 00004 01000 TIM 001 00005 #0015 001.5 s 0015 00006 01000 01000 TIM 001 00007 AND NOT 00204 00008 00204...
Page 130: High-Speed Timer - Timh(15)
Section 5-12 Timer and Counter Instructions A simpler but less flexible method of creating a flicker bit is to AND one of the SR area clock pulse bits with the execution condition that is to be ON when the flicker bit is operating. Although this method does not use TIM, it is in- cluded here for comparison.
Page 131: Counter - Cnt
Section 5-12 Timer and Counter Instructions The SV of the timers can be set in the range #0000 to #9999 (BCD). If the SV for a timer is set to #0000 or #0001, it will operate in the following way. If the SV is set to #0000, when the timer input goes from OFF to ON, the Com- pletion Flag will turn ON.
Page 132 Section 5-12 Timer and Counter Instructions Execution condition on count pulse (CP) Execution condition on reset (R) Completion Flag 0002 SV – 1 0001 SV – 2 0000 Precautions Program execution will continue even if a non-BCD SV is used, but the SV will not be correct.
Page 133 Section 5-12 Timer and Counter Instructions In the following example, 00000 is used to control when CNT 001 operates. CNT 001, when 00000 is ON, counts down the number of OFF to ON changes in 00001. CNT 001 is reset by its Completion Flag, i.e., it starts counting again as soon as its PV reaches zero.
Page 134: Reversible Counter - Cntr(12)
Section 5-12 Timer and Counter Instructions 00000 TIM 001 CNT 002 Address Instruction Operands TIM 001 00000 00000 #0050 005.0 s 00001 AND NOT TIM 001 00002 AND NOT 00003 00001 0050 #0100 00004 00005 00001 CNT 002 00201 00006 0100 00007 00008...
Page 135 Section 5-12 Timer and Counter Instructions The present value (PV) will be incremented by one whenever CNTR(12) is executed with an ON execution condition for II and the last execution condi- tion for II was OFF. The present value (PV) will be decremented by one whenever CNTR(12) is executed with an ON execution condition for DI and the last execution condition for DI was OFF.
Page 136: Data Shifting
Section 5-13 Data Shifting 5-13 Data Shifting All of the instructions described in this section are used to shift data, but in differing amounts and directions. The first shift instruction, SFT(10), shifts an execution condition into a shift register; the rest of the instructions shift data that is already in memory.
Page 137 Section 5-13 Data Shifting Example 1: The following example uses the 1-second clock pulse bit (25502) so that the Basic Application execution condition produced by 00005 is shifted into a 3-word register be- tween IR 010 and IR 012 every second. 00005 Address Instruction Operands...
Page 138: Reversible Shift Register - Sftr(84)
Section 5-13 Data Shifting used to detect faulty products in the shoot so that the pusher output and HR 0003 of the shift register can be reset as required. Sensor (00001) Pusher (00500) Sensor (00002) Rotary Encoder (00000) Chute Address Instruction Operands 00001 00000...
Page 139 Section 5-13 Data Shifting tion, the status to be put into the register, the shift pulse, and the reset input. The control word is allocated as follows: 15 14 13 12 Not used. Shift direction 1 (ON): Left (LSB to MSB) 0 (OFF): Right (MSB to LSB) Status to input into register Shift pulse bit...
Page 140: Arithmetic Shift Left - Asl(25)
Section 5-13 Data Shifting 5-13-3 ARITHMETIC SHIFT LEFT – ASL(25) Ladder Symbols Operand Data Areas Wd: Shift word ASL(25) @ASL(25) IR, AR, DM, HR, LR Description When the execution condition is OFF, ASL(25) is not executed. When the execution condition is ON, ASL(25) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one bit to the left, and shifts the status of bit 15 into CY.
Page 141: Rotate Left - Rol(27)
Section 5-13 Data Shifting 5-13-5 ROTATE LEFT – ROL(27) Ladder Symbols Operand Data Areas Wd: Rotate word ROL(27) @ROL(27) IR, AR, DM, HR, LR Description When the execution condition is OFF, ROL(27) is not executed. When the execution condition is ON, ROL(27) shifts all Wd bits one bit to the left, shift- ing CY into bit 00 of Wd and shifting bit 15 of Wd into CY.
Page 142: One Digit Shift Left - Sld(74)
Section 5-13 Data Shifting Indirectly addressed DM word is non-existent. (Content of *DM word Flags is not BCD, or the DM area boundary has been exceeded.) Receives the data of bit 15. ON when the content of Wd is zero; otherwise OFF. 5-13-7 ONE DIGIT SHIFT LEFT –...
Page 143: Word Shift - Wsft(16)
Section 5-13 Data Shifting Limitations St and E must be in the same data area, and E must be less than or equal to Description When the execution condition is OFF, SRD(75) is not executed. When the execution condition is ON, SRD(75) shifts data between St and E (inclusive) by one digit (four bits) to the right.
Page 144: Reversible Word Shift - Rws(17)
Section 5-13 Data Shifting Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) 5-13-10 REVERSIBLE WORD SHIFT – RWS(17) Operand Data Areas C: Control word Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # RWS(17) RWS(17) St: Starting word...
Page 145: Data Movement
Section 5-14 Data Movement be set to 0000. The data changes that would occur for the given register and control word contents are also shown. Before After execution execution DM 0100 1234 0000 HR 1213: OFF (Shift upward) HR 1214: ON (Shift enabled) DM 0101 0000 1234...
Page 146: Move Not - Mvn(22)
Section 5-14 Data Movement ON when all zeros are transferred to D. 5-14-2 MOVE NOT – MVN(22) Ladder Symbols Operand Data Areas S: Source word MVN(22) @MVN(22) IR, SR, AR, DM, HR, TC, LR, # D: Destination word IR, AR, DM, HR, LR Description When the execution condition is OFF, MVN(22) is not executed.
Page 147: Word-To-Column - Wtc
Section 5-14 Data Movement 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 S+15 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0...
Page 148: Block Set - Bset(71)
Section 5-14 Data Movement 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 D+15 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0...
Page 149 Section 5-14 Data Movement 3 4 5 3 4 5 St+1 3 4 5 St+2 3 4 5 3 4 5 BSET(71) can be used to change timer/counter PV. (This cannot be done with MOV(21) or MVN(22).) BSET(71) can also be used to clear sections of a data area, i.e., the DM area, to prepare for executing other instructions.
Page 150: Block Transfer - Xfer(70)
Section 5-14 Data Movement 5-14-6 BLOCK TRANSFER – XFER(70) Operand Data Areas N: Number of words (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # XFER(70) @XFER(70) S: Starting source word IR, SR, AR, DM, HR, TC, LR D: Starting destination word IR, AR, DM, HR, TC, LR Limitations...
Page 151: Single Word Distribute - Dist(80)
Section 5-14 Data Movement Description When the execution condition is OFF, XCHG(73) is not executed. When the execution condition is ON, XCHG(73) exchanges the content of E1 and E2. If you want to exchange content of blocks whose size is greater than 1 word, use work words as an intermediate buffer to hold one of the blocks using XFER(70) three times.
Page 152: Move Bit - Movb
Section 5-14 Data Movement Limitations Of must be a BCD. SBs must be in the same data area as SBs+Of. Description When the execution condition is OFF, COLL(81) is not executed. When the execution condition is ON, COLL(81) copies the content of SBs + Of to D, i.e., Of is added to SBs to determine the source word.
Page 153: Move Digit - Movd(83)
Section 5-14 Data Movement 5-14-11 MOVE DIGIT – MOVD(83) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MOVD(83) @MOVD(83) Di: Digit designator (BCD) IR, AR, DM, HR, TC, LR, # D: Destination word IR, AR, DM, HR, TC, LR Limitations The rightmost three digits of Di must each be between 0 and 3.
Page 154: Data Comparison
Section 5-15 Data Comparison 5-15 Data Comparison This section describes the instructions used for comparing data. CMP(20) is used to compare the contents of two words; BCMP(68) is used to determine within which of several preset ranges the content of one word lies; and TCMP(85) is used to determine which of several preset values the content of one word equals.
Page 155: Compare - Cmp(20)
Section 5-15 Data Comparison Example The following example shows the comparisons made and the results pro- vided for MCMP(19). Here, the comparison is made during each cycle when 00000 is ON. 00000 Address Instruction Operands MCMP(19) 00000 00000 00001 MCMP(19) DM 0200 DM 0300 0200...
Page 156 Section 5-15 Data Comparison Indirectly addressed DM word is non-existent. (Content of *DM word Flags is not BCD, or the DM area boundary has been exceeded.) ON if Cp1 equals Cp2. ON if Cp1 is less than Cp2. ON if Cp1 is greater than Cp2. Flag Address C1 <...
Page 157: Double Compare - Cmpl(60)
Section 5-15 Data Comparison Because all of the comparisons here use to the timer’s PV as reference, the other operand for each CMP(20) must be in 4-digit BCD. 00000 TIM 010 #5000 500.0 s CMP(20) TIM 010 #4000 25507 Output at 00200 100 s.
Page 158 Section 5-15 Data Comparison Limitations Can be performed with the CPU11-E only. Description When the execution condition is OFF, CMPL(60) is not executed. When the execution condition is ON, CMPL(60) joins the 4-digit hexadecimal content of Cp1+1 with that of Cp1, and that of Cp2+1 with that of Cp2 to create two 8-digit hexadecimal numbers, Cp+1,Cp1 and Cp2+1,Cp2.
Page 159: Block Compare - Bcmp(68)
Section 5-15 Data Comparison 5-15-4 BLOCK COMPARE – BCMP(68) Operand Data Areas CD: Compare data Ladder Symbols IR, SR, DM, HR, TC, LR, # BCMP(68) @BCMP(68) CB: First comparison block word IR, SR, DM, HR, TC, LR R: Result word IR, AR, DM, HR, TC, LR Limitations Each lower limit word in the comparison block must be less than or equal to...
Page 160 Section 5-15 Data Comparison Example The following example shows the comparisons made and the results pro- vided for BCMP(68). Here, the comparison is made during each cycle when 00000 is ON. 00000 Address Instruction Operands BCMP(68) 00000 00000 00001 BCMP(88) HR 10 HR 05 CD 001...
Page 161 Section 5-15 Data Comparison Example The following example shows the comparisons made and the results pro- vided for TCMP(85). Here, the comparison is made during each cycle when 00000 is ON. Address Instruction Operands 00000 TCMP(85) 00000 00000 00001 TCMP(85) HR 10 HR 05 CD: 001...
Page 162: Data Conversion
Section 5-16 Data Conversion 5-16 Data Conversion The conversion instructions convert word data that is in one format into an- other format and output the converted data to specified result word(s). Con- versions are available to convert between binary (hexadecimal) and BCD, to 7-segment display data, to ASCII, and between multiplexed and non-multi- plexed data.
Page 163: Binary-To-Bcd - Bcd(24)
Section 5-16 Data Conversion Description When the execution condition is OFF, BINL(58) is not executed. When the execution condition is ON, BINL(58) converts an eight-digit number in S and S+1 into 32-bit binary data, and outputs the converted data to R and R+1. S + 1 R + 1 Binary...
Page 164: Double Binary-To-Double Bcd - Bcdl(59)
Section 5-16 Data Conversion 5-16-4 DOUBLE BINARY-TO-DOUBLE BCD – BCDL(59) Ladder Symbols Operand Data Areas S: First source word (binary) BCDL(59) @BCDL(59) IR, SR, AR, DM, HR, LR R: First result word IR, AR, DM, HR, LR Limitations If the content of S exceeds 05F5E0FF, the converted result would exceed 99999999 and BCDL(59) will not be executed.
Page 165: Seconds-To-Hours - Sth(66)
Section 5-16 Data Conversion For the source data, the seconds is designated in bits 00 through 07 and the minutes is designated in bits 08 through 15 of S. The hours is designated in S+1. The maximum is thus 9,999 hours, 59 minutes, and 59 seconds. The results is output to R and R+1.
Page 166: 4-To-16 Decoder - Mlpx(76)
Section 5-16 Data Conversion For the results, the seconds is placed in bits 00 through 07 and the minutes is placed in bits 08 through 15 of R. The hours is placed in R+1. The maxi- mum will be 9,999 hours, 59 minutes, and 59 seconds. Flags S and S+1 or R and R+1 are not in the same data area.
Page 167 Section 5-16 Data Conversion then one bit will be turned ON in each of consecutive words beginning with R. (See examples, below.) The following is an example of a one-digit decode operation from digit num- ber 1 of S, i.e., here Di would be 0001. Source word Bit C (i.e., bit number 12) turned ON.
Page 168: 16-To-4 Encoder - Dmpx
Section 5-16 Data Conversion Flags Undefined digit designator, or R plus number of digits exceeds a data area. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) Example The following program converts three digits of data from DM 0020 to bit posi- tions and turns ON the corresponding bits in three consecutive words starting with HR 10.
Page 169 Section 5-16 Data Conversion All source words must be in the same data area. Description When the execution condition is OFF, DMPX(77) is not executed. When the execution condition is ON, DMPX(77) determines the position of the highest ON bit in S, encodes it into single-digit hexadecimal value corresponding to the bit number of the highest ON bit number, then transfers the hexadecimal value to the specified digit in R.
Page 170 Section 5-16 Data Conversion Some example Di values and the word-to-digit conversions that they produce are shown below. Di: 0011 Di: 0030 S + 1 S + 1 S + 2 S + 3 Di: 0013 Di: 0032 S + 1 S + 1 S + 2 S + 3...
Page 171: 7-Segment Decoder - Sdec(78)
Section 5-16 Data Conversion assumed that the bit with status 1 (ON) shown is the highest bit that is ON in the word. 00000 Address Instruction Operands DMPX(77) 00000 00000 00001 DMPX(77) HR 20 #0010 0010 DMPX(77) 00002 DMPX(77) LR 10 HR 20 #0012 0012...
Page 172 Section 5-16 Data Conversion half of D to receive the first 7-segment display code (rightmost or leftmost 8 bits) are designated in Di. If multiple digits are designated, they will be placed in order starting from the designated half of D, each requiring two digits. If more digits are designated than remain in S (counting from the designated first digit), further digits will be used starting back at the beginning of S.
Page 173 Section 5-16 Data Conversion The table underneath shows the original data and converted code for all hex- adecimal digits. Bit 00 bit 08 1: Second digit 0: One digit Bit 07 bit 15 0 or 1: bits 00 through 07 or 08 through 15.
Page 174: Ascii Convert - Asc(86)
Section 5-16 Data Conversion 5-16-10 ASCII CONVERT – ASC(86) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR ASC(86) @ASC(86) Di: Digit designator IR, AR, DM, HR, TC, LR, # D: First destination word IR, AR, DM, HR, LR Limitations Di must be within the values given below...
Page 175: Bcd Calculations
Section 5-17 BCD Calculations Some examples of Di values and the 4-bit binary to 8-bit ASCII conversions that they produce are shown below. Di: 0011 Di: 0030 1st half 1st half 2nd half 2nd half 1st half 2nd half Di: 0112 Di: 0130 1st half 1st half...
Page 176: Increment - Inc(38)
Section 5-17 BCD Calculations The addition and subtraction instructions include CY in the calculation as well as in the result. Be sure to clear CY if its previous status is not required in the calculation, and to use the result placed in CY, if required, before it is changed by execution of any other instruction.
Page 177: Clear Carry - Clc(41)
Section 5-17 BCD Calculations 5-17-4 CLEAR CARRY – CLC(41) Ladder Symbols CLC(41) @CLC(41) When the execution condition is OFF, CLC(41) is not executed.When the ex- ecution condition is ON, CLC(41) turns OFF CY (SR 25504). CLEAR CARRY is used to reset (turn OFF) CY (SR 25504) to “0”. 5-17-5 BCD ADD –...
Page 178: Double Bcd Add - Addl(54)
Section 5-17 BCD Calculations last digit is preserved in R+1 so that the entire result can be later handled as eight-digit data. Address Instruction Operands TR 0 00000 00002 00002 CLC(41) 00001 00002 CLC(41) 00003 AND(30) ADD(30) LR 25 6103 #6103 0100 DM 0100...
Page 179: Bcd Subtract - Sub(31)
Section 5-17 BCD Calculations Flags Au and/or Ad is not BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) ON when there is a carry in the result. ON when the result is 0.
Page 180 Section 5-17 BCD Calculations Flags Mi and/or Su is not BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) ON when the result is negative, i.e., when Mi is less than Su plus CY. ON when the result is 0.
Page 181 Section 5-17 BCD Calculations turned OFF for at least one cycle (resetting HR 2100) and then turned back TR 0 00002 CLC(41) @SUB(31) First subtraction DM 0100 HR 20 25504 CLC(41) @SUB(31) Second subtraction #0000 HR 20 Address Instruction Operands HR 21 00000 00002...
Page 182: Double Bcd Subtract - Subl(55)
Section 5-17 BCD Calculations Second Subtraction 0000 HR 20 –7577 –0 HR 20 2423 (0000 + (10000 – 7577)) (negative result) In the above case, the program would turn ON HR 2100 to indicate that the value held in HR 20 is negative. 5-17-8 DOUBLE BCD SUBTRACT –...
Page 183 Section 5-17 BCD Calculations and DM 0001 so that a negative result can be subtracted from 0 (inputting an 8-digit constant is not possible). TR 0 00003 CLC(41) @SUBL(55) First subtraction HR 20 DM 0100 25504 @BSET(71) #0000 DM 0000 DM 0001 CLC(41) Second...
Page 184: Bcd Multiply - Mul(32)
Section 5-17 BCD Calculations 5-17-9 BCD MULTIPLY – MUL(32) Operand Data Areas Md: Multiplicand (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MUL(32) @MUL(32) Mr: Multiplier (BCD) IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, AR, DM, HR LR Description When the execution condition is OFF, MUL(32) is not executed.
Page 185: Double Bcd Multiply - Mull(56)
Section 5-17 BCD Calculations 5-17-10 DOUBLE BCD MULTIPLY – MULL(56) Operand Data Areas Md: First multiplicand word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MULL(56) @MULL(56) Mr: First multiplier word (BCD) IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, AR, DM, HR LR Description...
Page 186: Double Bcd Divide - Divl(57)
Section 5-17 BCD Calculations is divided by Dr and the result is placed in R and R + 1: the quotient in R and the remainder in R + 1. Remainder Quotient Flags Dd or Dr is not in BCD. Indirectly addressed DM word is non-existent.
Page 187: Floating Point Divide - Fdiv(79)
Section 5-17 BCD Calculations divided by the content of Dr and Dr+1 and the result is placed in R to R+3: the quotient in R and R+1, the remainder in R+2 and R+3. Remainder Quotient Dr+1 Dd+1 Flags Dr and Dr+1 contain 0. Dd, Dd+1, Dr, or Dr+1 is not BCD.
Page 188 Section 5-17 BCD Calculations The mantissa is expressed as a value less than one, i.e., to seven decimal places. First word 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Exponent (0 to 7) Mantissa (leftmost 3 digits) Sign of exponent 0: +...
Page 189 Section 5-17 BCD Calculations 00000 @MOV(21) HR 01 HR 00 #0000 HR 00 @MOV(21) 0000 #0000 HR 02 @MOV(21) HR 01 HR 00 #4000 HR 01 @MOV(21) 4000 #4000 HR 03 DM 0000 @MOVD(83) DM 0000 #0021 HR 01 HR 00 HR 01 @MOVD(83) DM 0000...
Page 190: Square Root - Root(72)
Section 5-17 BCD Calculations 5-17-14 SQUARE ROOT – ROOT(72) Ladder Symbols Operand Data Areas Sq: First source word (BCD) ROOT(72) @ROOT(72) IR, SR, AR, DM, HR, TC, LR R: Result word IR, AR, DM, HR, LR, Description When the execution condition is OFF, ROOT(72) is not executed. When the execution condition is ON, ROOT(72) computes the square root of the eight-digit content of Sq and Sq+1 and places the result in R.
Page 191 Section 5-17 BCD Calculations 00000 @BSET(71) DM 0101 DM 0100 #0000 DM 0100 DM 0101 0000 0000 @MOV(21) DM 0101 DM 0101 DM 0100 @ROOT(72) DM 0100 60170000= 7756.932 DM 0102 @MOV(21) #0000 DM 0103 IR 011 @MOV(21) 0000 0000 #0000 DM 0103 @MOVD(83)
Page 192: Binary Calculations
Section 5-18 Binary Calculations 5-18 Binary Calculations The binary calculation instructions - ADB(50), SBB(51), MLB(52) and DVB(53) - all perform arithmetic operations on hexadecimal data. The addition and subtraction instructions include CY in the calculation as well as in the result. Be sure to clear CY if its previous status is not required in the calculation, and to use the result placed in CY, if required, before it is changed by the execution of any other instruction.
Page 193 Section 5-18 Binary Calculations In the case below, A6E2 + 80C5 = 127A7. The result is a 5-digit number, so CY (SR 25504) = 1, and the content of R + 1 becomes #0001. Au: IR 010 Ad: DM 0100 R+1: HR 11 R: HR 10 The following example performs eight-digit addition by using ADB(50) twice.
Page 194: Binary Subtract - Sbb(51)
Section 5-18 Binary Calculations In the case below, 4F52A6E2 + EC3B80C5 = 13B8E27A7. The sum of the lower 4-digit addition is a 5-digit number, so CY (SR 25504) = 1, and the sum of the higher 4-digit addition is incremented by 1. Lower 4 digits.
Page 195 Section 5-18 Binary Calculations HR 11, and either #0000 or #0001 is placed in HR 12 (0001 indicates a nega- tive answer). Address Instruction Operands TR 0 00000 00000 00000 CLC(41) 00001 00002 CLC(41) SBB(51) 00003 SBB(51) DM 0100 0100 HR 10 00004 SBB(51)
Page 196: Binary Multiply - Mlb(52)
Section 5-18 Binary Calculations #0000 – 6851 –1 (from CY = 1) = 0000 + (10000 – 6851 – 1) = 97AE. The content of HR 12, #0001, indicates a negative result. Lower 4 digits. Higher 4 digits. Mi: IR 010 Mi: IR 011 Su: DM 0100 Su: DM 0101...
Page 197: Logic Instructions
Section 5-19 Logic Instructions 5-18-4 BINARY DIVIDE – DVB(53) Operand Data Areas Dd: Dividend word (binary) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # DVB(53) @DVB(53) Dr: Divisor word (binary) IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, AR, DM, HR LR Description...
Page 198: Logical And - Andw
Section 5-19 Logic Instructions Indirectly addressed DM word is non-existent. (Content of *DM word Flags is not BCD, or the DM area boundary has been exceeded.) ON when the result is 0. 5-19-2 LOGICAL AND – ANDW(34) Operand Data Areas Ladder Symbols I1: Input 1 IR, SR, AR, DM, HR, TC, LR, #...
Page 199: Exclusive Or - Xorw
Section 5-19 Logic Instructions Example Indirectly addressed DM word is non-existent. (Content of *DM word Flags is not BCD, or the DM area boundary has been exceeded.) ON when the result is 0. 5-19-4 EXCLUSIVE OR – XORW(36) Operand Data Areas I1: Input 1 Ladder Symbols IR, SR, AR, DM, HR, TC, LR, #...
Page 200: Subroutines And Interrupt Control
Section 5-20 Subroutines and Interrupt Control 5-19-5 EXCLUSIVE NOR – XNRW(37) Operand Data Areas I1: Input 1 Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # XNRW(37) @XNRW(37) I2: Input 2 IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, AR, DM, HR, LR Description...
Page 201: Subroutine Define And Return - Sbn(92)/Ret(93
Section 5-20 Subroutines and Interrupt Control Whereas subroutine calls are controlled from within the main program, sub- routines activated by interrupts are triggered when the interrupt signal is re- ceived. Also, multiple interrupts from different Interrupt Input Units can occur at the same time.
Page 202: Subroutine Enter - Sbs(91)
Section 5-20 Subroutines and Interrupt Control 5-20-3 SUBROUTINE ENTER – SBS(91) Ladder Symbol Definer Data Areas N: Subroutine number SBS(91) N # (00 to 99) Description A subroutine can be executed by placing SBS(91) in the main program at the point where the subroutine is desired.
Page 203: Interrupt Control - Int
Section 5-20 Subroutines and Interrupt Control Although subroutines 00 through 31 can be called by using SBS(91), they are also activated by interrupt signals from Interrupt Input Units. Subroutine 99, which can also be called using SBS(91), is used for the scheduled inter- rupt.
Page 204 CC is 002. See below for details. INT(89) is used only to control the scheduled interrupts with the C200H and N must be set to 0004. Caution INT(89) cannot be used during execution of step programs or in C2000H Du- plex CPUs.
Page 205 Section 5-20 Subroutines and Interrupt Control Example The following program shows the overall structure and operation of the scheduled interrupt. Here, the scheduled subroutine is started and will be repeated every 20 ms. The control flow logic of the main program is unaffected by execution of the scheduled subroutine, i.e., immediately after the sub routine has finished execution, control returns to the point in the main pro- gram where it was suspended.
Page 206: 5-21 Step Instructions
Section 5-21 Step Instructions 5-21 Step Instructions The step instructions STEP(08) and SNXT(09) are used in conjunction to set up breakpoints between sections in a large program so that the sections can be executed as units and reset upon completion. A section of program will usually be defined to correspond to an actual process in the application.
Page 207 Section 5-21 Step Instructions timers in the step are reset to their SVs. Counters, shift registers, and bits used in KEEP(11) maintain status. Two simple steps are shown below. 00000 Starts step execution SNXT(09) LR 2000 STEP(08) LR 2000 Step controlled by LR 2000 1st step 00001 SNXT(09) LR 2001...
Page 208 Section 5-21 Step Instructions Flags 25407: Step Start Flag; turns ON for one cycle when STEP(08) is executed and can be used to reset counters in steps as shown below if neces- sary. 00000 Start SNXT(09) 01000 01000 STEP(08) 01000 00100 CNT 01 25407...
Page 209 Section 5-21 Step Instructions The following diagram demonstrates the flow of processing and the switches that are used for execution control. Process A Loading Process B Part Installation Process C Inspection/discharge The program for this process, shown below, utilizes the most basic type of step programming: each step is completed by a unique SNXT(09) that starts...
Page 210 Section 5-21 Step Instructions the next step. Each step starts when the switch that indicates the previous step has been completed turns ON. 00001 (SW1) Process A started. SNXT(09) 12800 STEP(08) 12800 Process A 00002 (SW2) Process A reset. SNXT(09) 12801 Process B started.
Page 211 Section 5-21 Step Instructions Example 2: The following process requires that a product is processed in one of two Branching Execution ways, depending on its weight, before it is printed. The printing process is the same regardless of which of the first processes is used. Various sensors are positioned to signal when processes are to start and end.
Page 212 Section 5-21 Step Instructions start either process A or process B. Both of the steps for these processes end with a SNXT(09) that starts the step for process C. 00001 (SW A1) 00002 (SW B2) SNXT(09) HR 0000 00001 (SW A1) 00002 (SW B2) SNXT(09) HR 0001 Process A started.
Page 213 Section 5-21 Step Instructions Example 3: The following process requires that two parts of a product pass simultane- Parallel Execution ously through two processes each before they are joined together in a fifth process. Various sensors are positioned to signal when processes are to start and end.
Page 214 Section 5-21 Step Instructions Process B is thus reset directly and process D is reset indirectly before exe- cuting the step for process E. 00001 (SW1 and SW2)) Process A started. SNXT(09) LR 0000 Process C started. SNXT(09) LR 0002 STEP(08) LR 0000 Process A 00002 (SW3)
Page 215: Special Instructions
Section 5-22 Special Instructions Address Instruction Operands Address Instruction Operands 00000 00001 00102 STEP(08) 0002 00001 SNXT(09) 0000 00002 SNXT(09) 0002 Process C 00003 STEP(08) 0000 00200 00003 Process A 00201 SNXT(09) 0003 00202 STEP(08) 0003 00100 00002 00101 SNXT(09) 0001 Process D 00102...
Page 216: Cycle Time - Scan(18)
Section 5-22 Special Instructions FAL(06) produces a non-fatal error and FAL(07) produces a fatal error. When FAL(06) is executed with an ON execution condition, the ALARM/ERROR indicator on the front of the CPU will flash, but PC operation will continue. When FALS(07) is executed with an ON execution condition, the ALARM/ER- ROR indicator will light and PC operation will stop.
Page 217: Message Display - Msg(46)
Section 5-22 Special Instructions 5-22-3 MESSAGE DISPLAY – MSG(46) Ladder Symbols Operand Data Areas FM: First message word MSG(46) @MSG(46) IR, AR, DM, HR, LR Description When executed with an ON execution condition, MSG(46) reads eight words of extended ASCII code from FM to FM+7 and displays the message on the Programming Console, GPC, or FIT.
Page 218: Long Message - Lmsg(47)
(00) into the string; no characters from the null character on will be output. D designates the destination of the output. For the C200H, 000 designates the Programming Console. To output to the Programming Console, it must be set in TERMINAL mode.
Page 219: Terminal Mode - Term(48)
Section 5-22 Special Instructions Flags S and S+15 are not in the same data area. Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) Example Although the display is longer and there is a choice of output devices, the coding LMSG(47) is the same as that for MSG(46).
Page 220: Bit Counter - Bcnt(67)
Section 5-22 Special Instructions Bit Control If the leftmost 8 bits of P contain A3, SYS(49) is used to set set system oper- ating parameters. To be effective, it must be programmed at program ad- dress 00001 with LD AR 1001 at program address 00000. Only bits 00, 06, and 07 are used.
Page 221 Section 5-22 Special Instructions Limitations Can be performed with the CPU11-E only. For trigonometric functions, x, the content of S, must be in BCD form and satisfy the condition 0000 ≤ x ≤ 0900 (0°≤Θ≤ 90°). Description When the execution condition is OFF, VCAL(69) is not executed. When the execution condition is ON, the operation of VCAL(69) depends on the control word C.
Page 222 Section 5-22 Special Instructions Linear Approximation VCAL(69) linear approximation is specified when C is a memory address. Word C is the first word of the continuous block of memory containing the linear approximation data. The content of word C specifies the number of line segments in the approxi- mation, and whether the input and output are in BCD or BIN form.
Page 223: Watchdog Timer Refresh- Wdt(94)
Section 5-22 Special Instructions In this case, the input data word, IR 010, contains #0014, and f(0014) = #0726 is output to R, IR 011. $1F20 $0F00 (x,y) $0726 $0402 (0,0) $0005 $0014 $001A $05F0 5-22-9 WATCHDOG TIMER REFRESH– WDT(94) Ladder Symbols Definer Data Areas T: Watchdog timer value...
Page 224: Sysmac Net Link/Sysmac Link Instructions
Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions Limitations IORF(97) can be used to refresh I/O words allocated to the CPU or an Ex- pansion I/O Rack only. It cannot be used for other I/O words. St must be less than or equal to E. Description When the execution condition is OFF, IORF(97) is not executed.
Page 225 Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions send data to a node on the same Subsystem (i.e., network). Refer to the SYSMAC NET Link System Manual for details. Word Bits 00 to 07 Bits 08 to 15 Number of words (0 to 1000 in 4-digit hexadecimal, i.e., 0000 to 03E8 Network number (0 to 127 in 2-digit Bit 14 ON: Operating level 0...
Page 226: Network Receive - Recv
Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) There is no SYSMAC NET Link/SYSMAC LINK Unit. 5-23-2 NETWORK RECEIVE – RECV(98) Operand Data Areas Ladder Symbols S: Source beginning word...
Page 227: About Sysmac Net Link/Sysmac Link Operations
Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions SYSMAC LINK Systems Refer to the SYSMAC LINK System Manual for details. Word Bits 00 to 07 Bits 08 to 15 Number of words (0 to 256 in 4-digit hexadecimal, i.e., 0000 to 0100 Response time limit (0.1 and 25.4 Bits 08 to 11: seconds in 2-digit hexadecimal...
Page 228 Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions If multiple SEND(90)/RECV(98) operations are used, the following flags must be used to ensure that any previous operation has completed before attempt- ing further send/receive SEND(90)/RECV(98) operations SR Flag Functions SEND(90)/RECV(98) OFF during SEND(90)/RECV(98) execution (including Enable Flags command response processing).
Page 229 Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions SEND(90)/RECV(98) Enable Flag 00000 25204 12802 12800 prevents execution of SEND(90) until RECV(98) (below) has completed. IR 00000 KEEP(11) is turned ON to start transmission. 12801 12800 12800 @MOV(21) #000A DM 0000 @MOV(21) #0000 DM 0001 Data is placed into control data words to...
Page 230 Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions Address Instruction Operands Address Instruction Operands 00000 00000 00019 AND NOT 12800 00001 25204 00020 12803 00002 AND NOT 12802 00021 KEEP(11) 12802 00003 12801 00022 12802 00004 KEEP(11) 12800 00023 25204 00005 12800 00024 AND NOT...
Page 231: Program Execution Timing
SECTION 6 Program Execution Timing The timing of various operations must be considered both when writing and debugging a program. The time required to execute the program and perform other CPU operations is important, as is the timing of each signal coming into and leav- ing the PC in order to achieve the desired control action at the right time.
Page 232: Cycle Time
Section 6-1 Cycle Time Cycle Time To aid in PC operation, the average, maximum, and minimum cycle times can be displayed on the Programming Console or any other Programming Device and the maximum cycle time and current cycle time values are held in AR 26 and AR 27.
Page 233: Cycle Time
Section 6-1 Cycle Time 6-1-1 CPU01-E, 03-E Cycle Time Power application Clears IR area and resets all timers Initialization on power-up Checks I/O Unit connections Resets watchdog timer Checks hardware and Program Memory Overseeing processes Check OK? Sets error flags and turns Link Unit ON or flashes indicator servicing...
Page 234: Cpu01-E, 03-E Cycle Time
Section 6-1 Cycle Time formed in cyclic fashion, with each scan forming one cycle. The cycle time is the time that is required for the CPU to complete one of these cycles. This cycle includes basically five types of operation. 1, 2, 3...
Page 235 Section 6-1 Cycle Time Special I/O Unit Refresh Unit Time required C200H-ID501/215 0.8 ms each C200H-OD501/215 0.8 ms each when set for 32 I/O pts. C200H-MD501/215 1.8 ms each when set for I/O timing C200H-CT001-V1/CT002 2.2 ms C200H-NC111/NC112 3.0 ms...
Page 236 Section 6-1 Cycle Time 6-1-2 CPU11-E Cycle Time Power application Clears IR area and resets all timers Initialization on power-up Checks I/O Unit connections Resets watchdog timer Overseeing Checks hardware and processes Program Memory Check OK? Resets watchdog timer and program address counter Sets error flags and turns ON or flashes indicator...
Page 237: Cpu11-E Cycle Time
Section 6-1 Cycle Time The first three operations immediately after power application are performed only once each time the PC is turned on. The rest of the operations are per- formed in cyclic fashion, with each scan forming one cycle. The cycle time is the time that is required for the CPU to complete one of these cycles.
Page 238: Calculating Cycle Time
Section 6-2 Calculating Cycle Time Even if the cycle time does not exceed the set value of the watchdog timer, a long cycle time can adversely affect the accuracy of system operations as shown in the following table. Cycle time (ms) Possible adverse affects 10 or greater TIMH(15) inaccurate when TC 016 through TC 511 are used.
Page 239: Calculating Cycle Time
Section 6-2 Calculating Cycle Time Calculations The equation for the cycle time from above is as follows: Cycle time = overseeing time + Link Unit servicing time + peripheral device servicing time + program execution time + I/O refreshing time The overseeing time is fixed at 2.6 ms.
Page 240: Instruction Execution Times
Instruction Execution Times The following table lists the execution times for all instructions that are avail- able for the C200H. The maximum and minimum execution times and the conditions which cause them are given where relevant. When “word” is referred to in the Conditions column, it implies the content of any word except for indirectly addressed DM words.
Page 241: Instruction Execution Times
Section 6-3 Instruction Execution Times µ µ Instruction Conditions ON execution time ( OFF execution time ( Constant for SV 2.25 2.25 2.25 JMP: 2.25 *DM for SV 2.25 JMP: 2.25 NOP(00) 0.75 END(01) IL(02) ILC(03) JMP(04) JME(05) FAL(06) 01 to 99 --- 2.25 FAL(06) 00 2.25...
Page 242 Section 6-3 Instruction Execution Times µ µ Instruction Conditions ON execution time ( OFF execution time ( SCAN(18) Constant for SV 3.75 *DM for SV MCMP(19) Comparing 2 words, result word 3.75 Comparing 2 *DM, result *DM CMP(20) When comparing a constant to a word When comparing two *DM MOV(21) When transferring a constant to a word...
Page 243 Section 6-3 Instruction Execution Times µ µ Instruction Conditions ON execution time ( OFF execution time ( DEC(39) When decrementing a word 2.25 When decrementing *DM STC(40) CLC(41) MSG(46) 2.25 LMSG(47) Constant for SV 3.75 *DM for SV TERM(48) 3.75 SYS(49) 3.75 ADB(50)
Page 244 Section 6-3 Instruction Execution Times µ µ Instruction Conditions ON execution time ( OFF execution time ( BCMP(68) Comparing constant to word-designated 3.75 table Comparing *DM b *DM-designated table VCAL69) Trigonometric functions. 3.75 Linear approximation with a 256 word 2.71 ms table XFER(70) When transferring 1 word...
Page 245 Section 6-3 Instruction Execution Times µ µ Instruction Conditions ON execution time ( OFF execution time ( ASC(86) Word b word 3.75 *DM b *DM INT(89) When reading interrupt mask 3.75 When masking and clearing interrupt SEND(90) 1-word transmit 3.75 1000-word transmit SBS(91) 2.25...
Page 246: I/O Response Time
Section 6-4 I/O Response Time I/O Response Time The I/O response time is the time it takes for the PC to output a control signal after it has received an input signal. The time it takes to respond depends on the cycle time and when the CPU receives the input signal relative to the in- put refresh period.
Page 247: I/O Response Time
Section 6-4 I/O Response Time Maximum I/O Response The PC takes longest to respond when it receives the input signal just after Time the I/O refresh phase of the cycle. In this case the CPU does not recognize the input signal until the end of the next cycle. The maximum response time is thus one cycle longer than the minimum I/O response time, except that the I/O refresh time would not need to be added in because the input comes just after it rather than before it.
Page 248: Program Monitoring And Execution
SECTION 7 Program Monitoring and Execution This section provides the procedures for monitoring and controlling the PC through a Programming Console. If you are using a GPC, a FIT, or a computer running LSS, refer to the Operation Manual for procedures on these. Monitoring Operation and Modifying Data .
Page 249: Monitoring Operation And Modifying Data
Section 7-1 Monitoring Operation and Modifying Data Monitoring Operation and Modifying Data The simplest form of operation monitoring is to display the address whose operand bit status is to be monitored using the Program Read or one of the search operations. As long as the operation is performed in RUN or MONI- TOR mode, the status of any bit displayed will be indicated.
Page 250 Section 7-1 Monitoring Operation and Modifying Data LD and OUT can be used only to designate the first address to be displayed; they cannot be used when an address is already being monitored. Key Sequence Clears leftmost address Cancels monitor operation Examples The following examples show various applications of this monitor operation.
Page 251: Monitoring Operation And Modifying Data
Section 7-1 Monitoring Operation and Modifying Data Bit Monitor Word Monitor...
Page 252 Section 7-1 Monitoring Operation and Modifying Data Multiple Address Monitoring Cancels monitoring of leftmost address Monitor operation canceled Indicates Force Reset in operation. Indicates Force Set in operation. 7-1-2 Forced Set/Reset When the Bit/Digit Monitor operation is being performed and a bit, timer, or counter address is leftmost on the display, PLAY/SET can be pressed to turn ON the bit, start the timer, or increment the counter and REC/RESET can be pressed to turn OFF the bit or reset the timer or counter.
Page 253 Section 7-1 Monitoring Operation and Modifying Data Bit status will remain ON or OFF only as long as the key is held down; the original status will return as soon as the key is released. If a timer is started, the completion flag for it will be turned ON when SV has been reached.
Page 254: Forced Set/Reset
Section 7-1 Monitoring Operation and Modifying Data The following displays show what happens when TIM 000 is set with 00100 OFF (i.e., 00500 is turned ON) and what happens when TIM 000 is reset with 00100 ON (i.e., timer starts operation, turning OFF 00500, which is turned back ON when the timer has finished counting down the SV).
Page 255: Hexadecimal/Bcd Data Modification
Section 7-1 Monitoring Operation and Modifying Data Example The following example shows the displays that appear when Restore Status is carried out normally. 7-1-4 Hexadecimal/BCD Data Modification When the Bit/Digit Monitor operation is being performed and a BCD or hexa- decimal value is leftmost on the display, CHG can be input to change the value.
Page 256: Hex/Ascii Display Change
Section 7-1 Monitoring Operation and Modifying Data Example The following example shows the effects of changing the PV of a timer. This example is in MONITOR mode Timing PV changed Timing Timing Timing 7-1-5 Hex/ASCII Display Change This operation converts DM data displays from 4-digit hexadecimal data to ASCII and vice versa.
Page 257 Section 7-1 Monitoring Operation and Modifying Data Example 7-1-6 3-word Monitor To monitor three consecutive words together, specify the lowest numbered word, press MONTR, and then press EXT to display the data contents of the specified word and the two words that follow it. A CLR entry changes the Three-word Monitor operation to a single-word dis- play.
Page 258 Section 7-1 Monitoring Operation and Modifying Data Example 7-1-7 3-word Data Modification This operation changes the contents of a word during the 3-Word Monitor operation. The blinking square indicates where the data can be changed. After the new data value is keyed in, pressing WRITE causes the original data to be overwritten with the new data.
Page 259: 3-Word Monitor
Section 7-1 Monitoring Operation and Modifying Data Example 3-word Monitor in progress. Stops in the middle of monitoring. Resumes previous monitoring. 7-1-8 Binary Monitor You can specify that the contents of a monitored word be displayed in binary by pressing SHIFT and MONTR after the word address has been input. Words can be successively monitored by using the up and down keys to in- crement and decrement the displayed word address.
Page 260: 3-Word Data Modification
Section 7-1 Monitoring Operation and Modifying Data Example Indicates Force Reset in effect Indicates Force Set in effect 7-1-9 Binary Data Modification This operation assigns a new 16-digit binary value to an IR, HR, AR, LR, or DM word. The cursor, which can be shifted to the left with the up key and to the right with the down key, indicates the position of the bit that can be changed.
Page 261 Section 7-1 Monitoring Operation and Modifying Data Key Sequence Word currently displayed in binary. (Force Status Clear)
Page 262: Changing Timer/Counter Sv
Section 7-1 Monitoring Operation and Modifying Data Example IR bit 00115 IR bit 00100 7-1-10 Changing Timer/Counter SV There are two ways to change the SV of a timer or counter. It can be done either by inputting a new value; or by incrementing or decrementing the cur- rent SV.
Page 263 Section 7-1 Monitoring Operation and Modifying Data This operation can be used to change a SV from designation as a constant to a word address designation and visa verse. Key Sequence Example The following examples show inputting a new constant, changing from a con- stant to an address, and incrementing to a new constant.
Page 264 Section 7-1 Monitoring Operation and Modifying Data Incrementing and Decrementing Current SV (during change operation) SV before the change Returns to original display with new SV...
Page 265: Program Backup And Restore Operations
Section 7-2 Program Backup and Restore Operations Program Backup and Restore Operations Both Program Memory (UM) and DM area data can be backed-up on a stan- dard, commercially available cassette tape recorder. Any dependable mag- netic cassette tape of adequate length will suffice. To save a 8K-word pro- gram, the tape must be about 15 minutes long (about 2 min.
Page 266 Section 7-2 Program Backup and Restore Operations Key Sequence [Start address] [File no.] WRITE Start recording with the [Stop address] WRITE SHIFT tape recorder. RESET After about 5 seconds** (Cancel with the CLR key). **These times take the cassette leader tape into consideration according to the following: a) When recording to tape, the leader tape needs to be allowed to pass before the data transmission to the tape player starts.
Page 267: Program Backup And Restore Operations
Section 7-2 Program Backup and Restore Operations Example Selecting Program Memory Starting address of data to be recorded Last address Stop address specified Start recording Continue within 5 seconds Blinking Recording in progress When it comes to END Stop recording with CLR Saved up to stop address 7-2-2 Restoring or Comparing Program Memory Data...
Page 268 Section 7-2 Program Backup and Restore Operations Specify the start address for the data that is to be restored or compared. Start playing the cassette tape. Within 5 seconds, press SHIFT and PLAY/SET to restore data or VER to compare data. Program restoration or comparison continues until END(01) is reached or until the tape is finished, at which time the program size in Kwords is dis- played.
Page 269: Restoring Or Comparing Program Memory Data
Section 7-2 Program Backup and Restore Operations Example Restoring in progress Comparison in progress END reached END reached Restored up to END Stop comparison using CLR Stop restoring using CLR Compared up to end of tape 7-2-3 Saving, Restoring, and Comparing DM Data The procedures for saving, restoring and comparing DM area data are identi- cal to those for Program Memory except that the DM area is specified and start and stop addresses are not required.
Page 270 Section 7-2 Program Backup and Restore Operations the preceding sections for details. An example for each operation is given below. Key Sequence 5 second leader tape** Start tape recorder re- Saving [File no.] SHIFT cording. RESET Start tape recorder PLAY Restoring SHIFT playback.
Page 271 Section 7-2 Program Backup and Restore Operations Example: Restoring DM Data Selecting the DM area Start tape playback Within 5 seconds Blinking Restoring in progress Restoring stopped using CLR key. Restoring stopped at the end.
Page 272 Section 7-2 Program Backup and Restore Operations Example: Comparing DM Data Selecting the DM area Start tape playback Within 5 seconds Blinking Comparison in progress Stopped verification using CLR Key Verification stopped at the end.
Page 273: Troubleshooting
SECTION 8 Troubleshooting The C200H provides self-diagnostic functions to identify many types of abnormal system conditions. These functions minimize downtime and enable quick, smooth error correction. This section provides information on hardware and software errors that occur during PC operation. Program input errors are described in 4-6 Inputting, Modifying, and Checking the Program.
Page 274: Alarm Indicators
Section 8-3 Reading and Clearing Errors and Messages Alarm Indicators The ALARM/ERROR indicator on the front of the CPU provides visual indica- tion of an abnormality in the PC. When the indicator is ON (ERROR), a fatal error (i.e., ones that will stop PC operation) has occurred; when the indicator is flashing (ALARM), a nonfatal error has occurred.
Page 275: Error Messages
Section 8-4 Error Messages Error Messages There are basically three types of errors for which messages are displayed: initialization errors, non-fatal operating errors, and fatal operating errors. Most of these are also indicated by FAL number being transferred to the FAL area of the SR area.
Page 276 Section 8-4 Error Messages POWER and RUN indicators will be lit and the ALARM/ERROR indicator will be flashing. The RUN output will be ON. Error and message FAL no. Probable cause Possible correction 01 to 99 FAL(06) has been executed Correct according to cause FAL error in program.
Page 277 Section 8-4 Error Messages other fatal operating errors, the POWER and ALARM/ERROR indicators will be lit. The RUN output will be OFF. Error and message FAL no. Probable cause Possible correction Power interruption None Power has been Check power supply voltage interrupted for at least and power lines.
Page 278: Error Flags
Section 8-5 Error Flags Other Error Messages A number of other error messages are detailed within this manual. Errors in program input and debugging can be examined in Section 4 and errors in cassette tape operation are detailed in Section 7-2. Error Flags The following table lists the flags and other information provided in the SR and AR areas that can be used in troubleshooting.
Page 279 Section 8-5 Error Flags AR Area Address(es) Function 0000 to 0009 Special I/O or PC Link Unit Error Flags 0010 SYSMAC LINK/SYSMAC NET Link Level 1 System Error Flags 0011 SYSMAC LINK/SYSMAC NET Link Level 0 System Error Flags 0012 Rack-mounting Host Link Unit Level 1 Error Flag 0013 Rack-mounting Host Link Unit Level 0 Error Flag...
Page 280: A Standard Models
Standard Models The C200H is a Rack-type PC that can be configured many different ways. Here is a series of tables listing the Units available for the C200H, along with a brief description of the Unit and its model number.
Page 281 B7A Interface Units 15 or Connects to B7A Link Terminals. C200H-B7AI1 16 input 16 out- C200H-B7AO1 put pts Note Transistor Output Unit C200H-OD212 and Contact Output Unit C200H- OC225 must be mounted to either a C200H-BC031-V2, C200H-BC051-V2, C200H-BC081-V2, or C200H-BC101-V2 Backplane.
Page 282 All of the following are classified as Special I/O Units except for the ASCII Unit, which is an Intelligent I/O Unit. Name Specifications Model number High- DC Input 32 pts 5 VDC (TTL inputs); with high-speed input function C200H-ID501 density I/O Units Units 32 pts 24 VDC; with high-speed inputs C200H-ID215...
Page 283 Note For Read/Write Head and Data Carrier combinations, refer to the V600 FA ID System R/W Heads and EE- PROM Data Carriers Operation Manual and Supplement or V600 FA ID System R/W Heads and SRAM Data Carriers Operation Manual and Supplement. C200H Link Units Name Specifications...
Page 284 12 pts. Connector Cover Protective cover for unused I/O Connecting Cable connectors C500-COV02 Space Unit Used for vacant slots C200H-SP001 Battery Set For C200H RAM Memory Unit only C200H-BAT09 Relay 24 VDC G6B-1174P-FD-US DC24 Backplane Insulation Plate For 10-slot Backplane C200H-ATTA1...
Page 285 APF/PCF. DIN Products Name Specifications Model number DIN Track Mounting Bracket 1 set (1 included) C200H-DIN01 DIN Track Length: 50 cm; height: 7.3 cm PFP-50N Length: 1 m; height: 7.3 cm PFP-100N Length: 1 m; height: 16 mm...
Page 286 Ambient temperature: 0° to 55°C (Must not be subjected to direct sunlight) Crystal Optical Fiber Cable (AGF) AGF stands for “All-Glass Fiber”. Crystal optical fiber cable is not available from OMRON. Cable Length The connectors may be difficult to attach to the cables. Therefore, always leave a little extra length when cutting the cable.
Page 287 C200H-CN422 Connecting Cables Data Setting Console C200H-DSC01 Used for data input and process value display for the C200H-TCjjj/C200H-TVjjj/C200H-PIDjj. Data Setting Console Con- For C200H-DSC01 C200H-CN225 necting Cables necting Cables C200H-CN425 Panel Mounting Bracket For vertical Programming Console, Data Access Console...
Page 288 SYSMAC LINK Unit/SYSMAC NET Link Unit If you are using any of the Units listed in the table below, they must be mounted to a CPU Rack that uses model C200H-CPU11-E as the CPU. Otherwise, these Units will not operate properly.
Page 289: B Programming Instructions
Appendix B Programming Instructions This appendix provides tables listing the programming instructions used with C200H PCs. The first table sum- marizes all instructions and gives page references where more detailed information can be found in the body of the manual. The second table gives the execution times for the instructions for both ON and OFF execution conditions.
Page 290 Appendix B Programming Instructions Function Code Name Mnemonic Page COMPARE MOVE MOVE NOT BCD-TO-BINARY BINARY-TO-BCD ARITHMETIC SHIFT LEFT ARITHMETIC SHIFT RIGHT ROTATE LEFT ROTATE RIGHT COMPLEMENT BCD ADD BCD SUBTRACT BCD MULTIPLY BCD DIVIDE AND WORD ANDW OR WORD EXCLUSIVE OR XORW EXCLUSIVE NOR XNRW...
Page 291 Appendix B Programming Instructions Function Code Name Mnemonic Page BLOCK SET BSET SQUARE ROOT ROOT DATA EXCHANGE XCHG ONE DIGIT SHIFT LEFT ONE DIGIT SHIFT RIGHT 4-TO-16 DECODER MLPX 16-TO-4 ENCODER DMPX 7-SEGMENT DECODER SDEC FLOATING POINT DIVIDE FDIV SINGLE WORD DISTRIBUTE DIST DATA COLLECT COLL...
Page 292 Programming Instructions Instruction Execution Times The following table lists the execution times for all instructions that are available for the C200H. The maximum and minimum execution times and the conditions which cause them are given where relevant. When “word” is referred to in the Conditions column, it implies the content of any word except for indirectly addressed DM words.
Page 293 Appendix B Programming Instructions µ µ Instruction Conditions ON execution time ( OFF execution time ( SNXT(09) 2.25 SFT(10) With 1-word shift register JMP: With 250-word shift register 1.44 ms 1.81 ms JMP: KEEP(11) 1.13 CNTR(12) Constant for SV *DM for SV JMP: DIFU(13) Normal: 93...
Page 294 Appendix B Programming Instructions µ µ Instruction Conditions ON execution time ( OFF execution time ( ASR(26) When shifting a word 2.25 When shifting *DM ROL(27) When rotating a word 2.25 When rotating *DM ROR(28) When rotating a word 2.25 When rotating *DM COM(29) When inverting a word...
Page 295 Appendix B Programming Instructions µ µ Instruction Conditions ON execution time ( OFF execution time ( ÷ DVB(53) 3.75 Word constant b word ÷ *DM b *DM ADDL(54) Word + word b word 3.75 *DM + *DM b *DM SUBL(55) Word –...
Page 296 Appendix B Programming Instructions µ µ Instruction Conditions ON execution time ( OFF execution time ( SLD(74) When shifting 1 word When shifting 1,000 DM words using *DM 33 ms SRD(75) When shifting 1 word When shifting 1,000 DM words using *DM 33 ms MLPX(76) When decoding word to word 3.75...
Page 297 Appendix B Programming Instructions Basic Instructions Name Symbol Function Operand Data Areas Mnemonic Logically ANDs the status of the desig- nated bit with the current execution condi- tion. AND LOAD Logically ANDs the resultant execution None AND LD conditions of the preceding logic blocks. AND NOT Logically ANDs the inverse of the desig- AND NOT...
Page 298 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic OR LOAD Logically ORs the resultant execution con- None OR LD ditions of the preceding logic blocks. OR NOT Logically ORs the inverse of the desig- OR NOT nated bit with the execution condition. OUTPUT Turns ON B for an ON execution condition;...
Page 299 Appendix B Programming Instructions Special Instructions Name Symbol Function Operand Data Areas Mnemonic NO OPERATION Nothing is executed and program opera- None NOP(00) tion moves to the next instruction. None Required at the end of each program. In- None END(01) structions located after END(01) will not be END(01) executed.
Page 300 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic STEP DEFINE When used with a control bit (B), defines STEP(08) the start of a new step and resets the pre- vious step. When used without B, it defines STEP(08) the end of step execution.
Page 301 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic WORD SHIFT The data in the words from the starting St/E: (@)WSFT(16) word (St) through to the ending word (E), is shifted left in word units, writing all zeros WSFT(16) into the starting word.
Page 302 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic MOVE Transfers data from source word, (S) to (@)MOV(21) destination word (D). MOV(21) MOVE NOT Transfers the inverse of the data in the (@)MVN(22) source word (S) to destination word (D). MVN(22) BCD-TO-BINARY Converts 4-digit, BCD data in source word...
Page 303 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic ARITHMETIC SHIFT Each bit within a single word of data (Wd) RIGHT is shifted one bit to the right, with zero writ- (@)ASR(26) ten to bit 15 and bit 00 moving to CY. ASR(26) ROTATE LEFT Each bit within a single word of data (Wd)
Page 304 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic BCD DIVIDE Divides the 4-digit BCD dividend (Dd) by Dd/Dr: (@)DIV(33) the 4-digit BCD divisor (Dr), and outputs DIV(33) the result to the specified result words. R receives the quotient; R + 1 receives the remainder.
Page 305 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic DECREMENT Decrements the value of a 4-digit BCD (@)DEC(39) word by 1, without affecting carry (CY). DEC(39) SET CARRY Sets the Carry Flag (i.e., turns CY ON). None (@)STC(40) STC(40) CLEAR CARRY Clears the Carry Flag (i.e, turns CY OFF).
Page 306 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic SET SYSTEM Used to either control certain operating –––: Not used. (@)SYS(49) parameters, or to execute the system SYS(49) (CPU11-E) commands that can be executed from the AR area. –––...
Page 307 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic BINARY DIVIDE Divides the 4-digit hexadecimal dividend Dd/Dr: (@)DVB(53) (Dd) by the 4-digit divisor (Dr), and outputs DVB(53) result to the designated result words ( R and R + 1). R and R + 1 must be in the same data area.
Page 308 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic DOUBLE BCD Multiplies the 8-digit BCD multiplicand and Md/Mr: MULTIPLY 8-digit BCD multiplier, and outputs the re- MULL(56) (@)MULL(56) sult to the specified result words. All words for any one operand must be in the same data area.
Page 309 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic DOUBLE Converts the binary value of the two BINARY-TO-DOUBLE source words (S: starting word) into eight BCDL(59) digits of BCD data, and outputs the con- (@)BCDL(59) verted data to the two result words (R: starting result word).
Page 310 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic Places bit data from the source word (S), WORD-TO-COLUMN consecutively into the same numbered (@)WTC(64) WTC(64) bits of the 16 consecutive destination (CPU11-E) words (where D is the address of the first destination word).
Page 311 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic BLOCK COMPARE Compares a 1-word binary value (S) with (@)BCMP(68) the 16 ranges given in the comparison BCMP(68) table (CB is the starting word of the com- parison block). If the value falls within any of the ranges, the corresponding bits in the result word (R) will be set.
Page 312 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic Calculates the cosine, or sine of the given VALUE CALCULATE degree value, or determines the y-coordi- (@)VCAL(69) VCAL(69) nate of the given x value in a previously es- (CPU11-E) tablished line graph.
Page 313: E Data Areas
Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic BLOCK TRANSFER Moves the content of several consecutive (@)XFER(70) source words (S gives the address of the XFER(70) starting source word) to consecutive desti- nation words (D is the starting destination word).
Page 314 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic ONE DIGIT SHIFT LEFT Shifts all data, between the starting word St/E: (@)SLD(74) (St) and ending word (E), one digit (four bits) to the left, writing zero into the right- SLD(74) most digit of the starting word.
Page 315 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic 7-SEGMENT DECODER Converts hexadecimal values from the (@)SDEC(78) source word (S) into 7-segment display SDEC(78) data. Results are placed in consecutive half-words, starting at the first destination word (D). Di gives digit and destination de- tails.
Page 316 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic DATA COLLECT Extracts data from the source word and SBs: (@)COLL(81) writes it to the destination word (D). The COLL(81) source word is determined by adding the offset (Of) to the address of the source base word (SBs).
Page 317 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic REVERSIBLE SHIFT Shifts bits in the specified word or series of St/E/C: REGISTER words either left or right. Starting (St) and SFTR(84) (@)SFTR(84) ending words (E) must be specified. Con- trol word (C) contains shift direction, reset input, and data input.
Page 318 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic ASCII CONVERT Converts hexadecimal digits from the (@)ASC(86) source word (S) into 8-bit ASCII values, ASC(86) starting at leftmost or rightmost half of the starting destination word (D). The right- most digit of Di designates the first source digit.
Page 319 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic NETWORK SEND Transfers data from n source words (S is D/C: (@)SEND(90) the starting word) to the destination words (CPU11-E) SEND(90) (D is the first address) in node N of the spe- cified network (in a SYSMAC LINK or NET Link System).
Page 320 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic SUBROUTINE START Marks the start of subroutine N. SBN(92) 00 to 99 SBN(92) RETURN Marks the end of a subroutine and returns None RET(93) control to the main program. RET(93) WATCHDOG TIMER Sets the maximum and minimum limits for...
Page 321 Appendix B Programming Instructions Name Symbol Function Operand Data Areas Mnemonic NETWORK RECEIVE Transfers data from the source words (S is C/D: (@)RECV(98) the first word) from node N of the specified (CPU11-E) RECV(98) network (in a SYSMAC LINK or NET Link System) to the destination words starting at D.
Page 322 Appendix C Programming Console Operations The table below lists the Programming Console operations, a brief description, and the page on which they appear in the body of this manual. All operations are described briefly, and the key sequence for inputting them given, in the tables which form the second part of this appendix.
Page 323 Appendix C Programming Console Operations System Operations Operation/Description Modes* Key sequence Password Input R M P Controls access to the PC’s program- MONTR ming functions. To gain access to the system once “PASSWORD” has been displayed, press CLR, MONTR, and then CLR. Buzzer ON/OFF R M P The buzzer can be switched to oper-...
Page 324 Unit type, location, I/O word allocation, and word multiplier (where applicable). Rack and unit To select Remote I/O Slave C200H Racks or Optical I/O Units numbers will vary according to the system in use. The EXT key can be...
Page 325 Appendix C Programming Console Operations Programming Operations Operation/Description Modes* Key sequence Address Designation R P M Displays the specified address. Can [Address] be used to start programming from a non-zero address or to access an ad- dress for editing. Leading zeros need not be entered.
Page 326 Appendix C Programming Console Operations Operation/Description Modes* Key sequence Instruction Insert and [Enter new At the desired position Instruction Delete Insert in program: instruction] The displayed instruction can be de- leted, or another instruction can be inserted before it. Care should be tak- Instruction en to avoid inadvertent deletions as currently...
Page 327 Appendix C Programming Console Operations Monitoring and Data Changing Operations Operation/Description Modes* Key sequence Bit/Word Monitor R P M Up to six memory addresses, con- CONT taining either words or bits, or a com- [Address] SHIFT bination of the two, can be monitored at once.
Page 328 There are two types of changes on PLAY SHIFT the C200H, temporary and perma- nent. Temporary changes result if 1 or 0 is entered. Permanent changes SHIFT are made by pressing SHIFT and RESET SET, or SHIFT and RESET.
Page 329 Appendix C Programming Console Operations Operation/Description Modes* Key sequence 3-word Change This operation changes the value of 3-word Monitor [Data] WRITE a word displayed during a 3-word in progress Monitor operation. The blinking cur- sor indicates the word that will be af- fected by the operation.
Page 330 Appendix C Programming Console Operations Cassette Tape Operations Operation/Description Modes* Key sequence Program Memory Save Copies data from the Program [Start address] [File no.] WRITE Memory to tape. The file no. specified in the instructions provides an identi- fying address for the information within the tape.
Page 331 Appendix C Programming Console Operations Operation/Description Modes* Key sequence Program Memory Compare The procedure to compare Program [Start address] [File no.] WRITE Memory data stored on a tape with that in the PC’s Program Memory area is the same as that for reading it (see above), except that after starting Start tape recorder the tape playback, VER should be...
Page 332 Appendix D Error and Arithmetic Flag Operation The following table shows the instructions that affect the ER, CY, GT, LT and EQ flags. In general, ER indi- cates that operand data is not within requirements. CY indicates arithmetic or data shift results. GT indicates that a compared value is larger than some standard, LT that it is smaller, and EQ, that it is the same.
Page 333 Appendix D Error and Arithmetic Flag Operation Instructions 25503 (ER) 25504 (CY) 25505 (GR) 25506 (EQ) 25507 (LE) MUL(32) Unaffected Unaffected Unaffected DIV(33) ANDW(34) ORW(35) XORW(36) XNRW(37) INC(38) DEC(39) STC(40) Unaffected Unaffected Unaffected Unaffected CLC(41) Unaffected Unaffected Unaffected Unaffected MSG(46) Unaffected Unaffected Unaffected...
Page 334 Appendix D Error and Arithmetic Flag Operation Instructions 25503 (ER) 25504 (CY) 25505 (GR) 25506 (EQ) 25507 (LE) XCHG(73) Unaffected Unaffected Unaffected Unaffected SLD(74) SRD(75) MLPX(76) DMPX(77) SDEC(78) FDIV(79) DIST(80) COLL(81) MOVB(82) MOVD(83) SFTR(84) Unaffected Unaffected Unaffected TCMP(85) Unaffected Unaffected Unaffected ASC(86) Unaffected...
Page 335 Appendix E Data Areas The data areas in the C200H are summarized below. Prefixes are included with bit and word addresses when inputting them is required to designate the area, i.e., bits/words input without a prefix are considered to be IR or SR bits/words.
Page 336 Appendix E Data Areas Dedicated Bits Most of the bits in the SR and AR area are dedicated for specific purposes. These are summarized in the fol- lowing tables. Refer to 3-4 SR Area and 3-5 AR Area for details. SR Allocations As a rule, SR area bits can be used only for the purposes for which they are dedicated.
Page 337 Appendix E Data Areas Word(s) Bit(s) Function Remote I/O Error Flag Normally ON Flag Normally OFF Flag First cycle 1-minute clock pulse bit 0.02-second clock pulse bit 02 to 06 Reserved for function expansion. Do not use. Step Flag 08 to 14 Reserved for function expansion.
Page 338 Appendix E Data Areas Word(s) Bit(s) Function 14/15 Remote I/O Master Unit 1/Unit 0 Restart Bits 00 to 04 Error Flags for Slave Racks 0 to 4 05 to 15 Not used. 00 to 15 Error Flags for Optical I/O Units 0 to 7 00 to 15 Error Flags for Optical I/O Units 8 to 15 00 to 15...
Page 339: F Word Assignment Recording Sheets
Appendix F Word Assignment Recording Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments, as well as details of work bits, data storage areas, timers, and counters.
Page 340 I/O Bits Programmer: Program: Date: Page: Word: Unit: Word: Unit: Field device Notes Field device Notes Word: Unit: Word: Unit: Field device Notes Field device Notes...
Page 341 Work Bits Programmer: Program: Date: Page: Area: Word: Area: Word: Usage Notes Usage Notes Area: Word: Area: Word: Usage Notes Usage Notes...
Page 342 Data Storage Programmer: Program: Date: Page: Word Contents Notes Word Contents Notes...
Page 343 Timers and Counters Programmer: Program: Date: Page: TC address T or C Set value Notes TC address T or C Set value Notes...
Page 344: G Program Coding Sheet
Appendix G Program Coding Sheet The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility, al- lowing the user to input all required addresses and instructions. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands.
Page 345 Program Coding Sheet Programmer: Program: Date: Page: Address Instruction Operand(s) Address Instruction Operand(s) Address Instruction Operand(s)
Page 346: H Data Conversion Table
Appendix H Data Conversion Table Decimal Binary 00000000 00000000 00000001 00000001 00000010 00000010 00000011 00000011 00000100 00000100 00000101 00000101 00000110 00000110 00000111 00000111 00001000 00001000 00001001 00001001 00010000 00001010 00010001 00001011 00010010 00001100 00010011 00001101 00010100 00001110 00010101 00001111 00010110 00010000 00010111 00010001...
Page 347: Extended Ascii
Appendix I Extended ASCII Programming Console and Data Access Console Displays Bits 0 to 3 Bits 4 to 7 0000 0001 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 0000 Space 0001 0010 0011 0100 0101 0110 0111 1000...
Page 348 Glossary address The location in memory where data is stored. For data areas, an address consists of a two-letter data area designation and a number that designates the word and/or bit location. For the UM area, an address designates the in- struction location (UM area).
Page 349 Glossary cial purposes, such as holding the status input from external devices, while other bits are available for general use in programming. bit address The location in memory where a bit of data is stored. A bit address must specify (sometimes by default) the data area and word that is being ad- dressed, as well as the number of the bit.
Page 350 Glossary Control System All of the hardware and software components used to control other devices. A Control System includes the PC System, the PC programs, and all I/O de- vices that are used to control or obtain feedback from the controlled system. controlled system The devices that are being controlled by a PC System.
Page 351 Glossary default A value automatically set by the PC when the user omits to set a specific val- ue. Many devices will assume such default conditions upon the application of power. definer A number used as an operand for an instruction but that serves to define the instruction itself, rather that the data on which the instruction is to operate.
Page 352 Glossary are usually the ON/OFF states of bits, or the logical combination of such states, called execution conditions. exection condition The ON or OFF status under which an instruction is executed. The execution condition is determined by the logical combination of conditions on the same instruction line and up to the instruction currently being executed.
Page 353 Glossary Graphic Programming A programming device with advanced programming and debugging capabili- Console ties to facilitate PC operation. A Graphic Programming Console is provided with a large display onto which ladder-diagram programs can be written di- rectly in ladder-diagram symbols for input into the PC without conversion to mnemonic form.
Page 354 Glossary instruction A direction given in the program that tells the PC of an action to be carried out, and which data is to be used in carrying out the action. Instructions can be used to simply turn a bit ON or OFF, or they can perform much more com- plex actions, such as converting and/or transferring large blocks of data.
Page 355 Glossary PC controlling the Master and a PC connected to the Remote I/O System through an I/O Link Unit or an I/O Link Rack. I/O Link Unit A Unit used with certain PCs to create an I/O Link in an Optical Remote I/O System.
Page 356 Glossary Link Adapter A Unit used to connect communications lines, either to branch the lines or to convert between different types of cable. There are two types of Link Adapter: Branching Link Adapters and Converting Link Adapters. link A hardware or software connection formed between two Units. “Link” can refer either to a part of the physical connection between two Units (e.g., opti- cal links in Wired Remote I/O Systems) or a software connection created to data existing at another location (Network Data Links).
Page 357 The device at a node is identified by the node number. One loop of a Net Link System (OMRON’s LAN) can consist of up to 126 nodes. Each node is occupied by a Net Link Unit mounted to a PC or a device providing an interface to a computer or other peripheral device.
Page 358 Glossary A logic operation which inverts the status of the operand. For example, AND NOT indicates an AND operation with the opposite of the actual status of the operand bit. An acronym for Network Service Board. An acronym for Network Service Unit. The status of an input or output when a signal is said not to be present.
Page 359: Glossary
Glossary output bit A bit in the IR area that is allocated to hold the status to be sent to an output device. output device An external device that receives signals from the PC System. output point The point at which an output leaves the PC System. Output points corre- spond physically to terminals or connector pins.
Page 360 Glossary Printer Interface Unit A Unit used to interface a printer so that ladder diagrams and other data can be printed out. program The list of instructions that tells the PC the sequence of control actions to be carried out. Programmable Controller A computerized device that can accept inputs from external devices and gen- erate outputs to external devices according to a program held in memory.
Page 361 Glossary Remote I/O Master Unit The Unit in a Remote I/O System through which signals are sent to all other Remote I/O Units. The Remote I/O Master Unit is mounted either to a CPU Rack or an Expansion I/O Rack connected to the CPU Rack. Remote I/O Master Unit is generally abbreviated to Master.
Page 362 Glossary The process of turning a bit or signal ON. set value The value from which a decrementing counter starts counting down or to which an incrementing counter counts up (i.e., the maximum count), or the time from which or for which a timer starts timing. Set value is abbreviated shift register One or more words in which data is shifted a specified number of units to the right or left in bit, digit, or word units.
Page 363 Unit In OMRON PC terminology, the word Unit is capitalized to indicate any prod- uct sold for a PC System. Though most of the names of these products end with the word Unit, not all do, e.g., a Remote Terminal is referred to in a col- lective sense as a Unit.
Page 364 Glossary watchdog timer A timer within the system that ensures that the cycle time stays within speci- fied limits. When limits are reached, either warnings are given or PC opera- tion is stopped depending on the particular limit that is reached. Wired Slave Rack A Slave Rack connected through a Wired Remote I/O Slave Unit.
Page 365: Index
Index counters bits in TC area, 40 changing SV, 251 addresses, in data area, 17 conditions when reset, 118, 122 creating extended timers, 120 applications, precautions, xv extended, 119 AR area, 32–37 inputting SV, 74 arithmetic flags, 98 Power-OFF, 36 reversible counters, 121 arithmetic operations, flags, 31 ASCII, converting data, 161...
Page 366 Index displays Network Parameter, 37 converting between hex and ASCII, 245 Optical Transmitting I/O Error, 33 I/O Unit designations, 68 Step, 31 Programming Console, English/Japanese switch, 62 floating-point decimal, division, 174 DM area, saving, restoring, and comparing, 258–261 Floppy Disk Interface Unit. See peripheral devices forced set/reset, 241 canceling, 243–244 Forced Status Hold Bit, 27...
Page 367 Index combining with OR, 49 MUL(32), 171 MULL(56), 172 AND LD, 51, 103 combining with OR LD, 54 MVN(22), 133 NOP(00), 112 use in logic blocks, 52 AND NOT, 48, 102 NOT, 45 operands, 44 ANDW(34), 185 OR, 48, 103 ASC(86), 161 combining with AND, 49 ASL(25), 127...
Page 368 Index monitoring J–L binary, 248 monitoring 3 words, 246 jump numbers, 110 mounting Units, location, 13 jumps, 110–111 ladder diagram branching, 83 IL(02) and ILC(03), 85 using TR bits, 83 nesting, subroutines, 189 controlling bit status NET Link System, LR area application. See SYSMAC NET using DIFU(13) and DIFD(14), 89, 105–106 Link System using KEEP(11), 106–112...
Page 369 Index PROM Writer, 6 status indicators. See CPU indicators servicing, 222 step execution, Step flag, 31 power supply, Power-OFF Counter, 36 step instructions, 193–202 precautions, xiii subroutine number, 188 applications, xv subroutines, 187–192 general, xiv operating environment, xv safety, xiv accessing via TC area, 41 changing, 251 present value.
Page 370: Revision History
Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W130-E1-05 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version.
Page 371 Revision History Revision Date Revised content code June 2003 Page xiv: Precautions added. Pages 21, 28, and 330: ”Data Retention Control Bit” unified to ”I/O Status Hold Bit.” Pages 28 and 29: Section added on operation without a battery.
Page 372 Wegalaan 67-69, NL-2132 JD Hoofddorp The Netherlands Tel: (31)2356-81-300/Fax: (31)2356-81-388 OMRON ELECTRONICS LLC 1 East Commerce Drive, Schaumburg, IL 60173 U.S.A. Tel: (1)847-843-7900/Fax: (1)847-843-8568 OMRON ASIA PACIFIC PTE. LTD. 83 Clemenceau Avenue, #11-01, UE Square, Singapore 239920 Tel: (65)6835-3011/Fax: (65)6835-2711...
Page 373 Authorized Distributor: Cat. No. W130-E1-05 Note: Specifications subject to change without notice. 0666362-6A Printed in Japan...

Omron C200H Operation Manual

Table of Contents

Precautions

Introduction

Hardware Considerations

Section 3 Memory Areas

Section 4 Writing and Inputting the Program

Section 5 Instruction Set

Section 6 Program Execution Timing

Section 7 Program Monitoring and Execution

Program Monitoring and Execution

Troubleshooting

Quick Links

Chapters

Related Manuals for Omron C200H

Summary of Contents for Omron C200H