Memory Modules; Persistent Memory - SMART Embedded Computing ATCA-F140 Series Installation And Use Manual

4.3.3

Memory Modules

The ATCA-F140 requires very low profile (VLP) DDR3 DIMM modules to fit within the
maximum component height profile of an ATCA blade. The ATCA-F140 comes standard
with a 2GB SG572568EMR069P2SG module from Smart Modular. Operation with other
memory modules is not guaranteed.
Each DIMM module has a serial presents detect (SPD) SROM that provides all necessary
information (such as speed, size and type) to the boot firmware. The SPD SROM is read
using the I
4.3.4

Persistent Memory

Persistent memory is part of the ATCA-F140 DDR memory subsystem. A dedicated register
is available in the FPGA to enable or disable persistent memory by software. If persistent
memory is enabled, the memory contents of the main memory stays unchanged after any
applied reset, except power-up reset. After power-up reset, the persistent memory features
is disabled by default.
A special procedure is followed to use the persistent memory feature.
 Set DDR_SDRAM_CFG_2[SR_IE] bit inside the memory controller of the QorIQ
P2020Integrated Processor.
 Set these fields in the programmable interrupt controller (PIC) of QorIQ P2020
Integrated Processor.
–
–

Enable persistent memory feature by setting persistent memory bit inside the
FPGA.
 Any reset may occur except for power-up reset.

The FPGA generates and interrupt (IRQ_L[11]) to the QorIQ P2020 Integrated
Processor.
 This external interrupt is steered through the PIC of QorIQ P2020 Integrated
Processor to the IRQ_OUT signal.
 The IRQ_OUT signal from the interrupt controller is then automatically detected by
the DDR controller, which immediately causes main memory to enter self-refresh
mode.
 1ms after the interrupt signal (IRQ_L[11]) the FPGA asserts the reset signal for at
least 50ms.
 Read persistent memory bit in FPGA.
 Initialize main memory but do not clear persistent memory area.
ATCA-F140 Series Installation and Use (6806800M67S)
2
C bus that is connected to the processor.
EIVPRn[PRIORITY] to 0xF (highest priority)
EIDRn[EP]
Functional Description
93