Post Routines; Table 5-5 Sys Fw Progress Ipmi Sensor - Post Error Event Codes - SMART Embedded Computing ATCA-F140 Series Installation And Use Manual

U-Boot
Table 5-5
Event Data (Byte 3)
0x1E
0x03
0x20
0x1F
0x0A
0x16
0x09
0x21
0x22
5.8.1

POST Routines

The following table describes that POST routines are performed.
Table 5-6
Device
CPU
FPGA
DRAM
Switch devices
Base interface
extender/SPI
2
I C buses
RTC
120
SYS FW PROGRESS IPMI Sensor - POST Error Event Codes
Description
Error accessing the switch devices
Error in network loop back test
Error in network PHY test
Error in glue logic (FPGA) test
2
Error in I C bus test
Error in RTC test
Error in flash test
Error in CPU test
Error in PCI bus test
POST Routines
Description
Check PLL configuration (PORPLLSR register).
Check device configuration (PORDEVSR register)
Register sanity check. The version code is checked. It must not be
0x00 or 0xFF.
Address line and data-line test.
The PCI interface is checked as follows:
Check for configuration space access (vendor/device ID)
Perform walking-one test on first memory-mapped register
Data test on LED register page 0, offset 0x12
Check whether bus addresses 0x50,0x51, 0x52 are accessible on bus
0 and 0x50, 0x6E on bus 1.
Checks whether the second counter is advancing.
Compares the number of CPU ticks in one second against the
expected system clock frequency (66 MHz)
ATCA-F140 Series Installation and Use (6806800M67S)
U-Boot