Service Processor Core Reset Domain; 4.11.1.1 Service Processor; Table 4-8 Reset Sources Versus Reset Outputs - SMART Embedded Computing ATCA-F140 Series Installation And Use Manual

Functional Description
A software controlled reset register within the FPGA provides software controlled resets to
the FIX, BIX and PHY functions. The FPGA also implements a last reset register to capture
the source of the last reset generated on the blade. The various on-board devices get reset
by the sources as shown in the following table.
Table 4-8
Reset Output
Reset Source
BRD_PWROK
PAYLOAD_RST_L
PB_RST_L
HRST_REQ_L
COP_HRESET_L
COP_SRESET_L
AMC_EN
AMC_PWR_GOOD
Software Control in
FPGA
4.11.1

Service Processor Core Reset Domain

The service processor core includes the QorIQ P2020 Integrated Processor, its memory
and the on-board resources attached to the local bus.

4.11.1.1 Service Processor

The hard reset signal HRST_L causes the QorIQ P2020 Integrated Processor to abort all
current internal and external transactions and set all registers to their default values.
HRST_L may be asserted at any time completely asynchronously. HRST_L needs to be
asserted during power-on reset. During HRST_L assertion, the configuration input signals
are sampled into registers inside the QorIQ P2020 Integrated Processor.
108
Reset Sources Versus Reset Outputs
Yes No
Yes No
Yes No
Yes No
Yes No
No
No No
No No
No No
Yes Yes Yes Yes
Yes Yes Yes Yes
Yes Yes Yes Yes
No No No No
Yes Yes Yes Yes
No No No No
No No No No
No No No No
Yes Yes Yes Yes
ATCA-F140 Series Installation and Use (6806800M67S)
Functional Description
Yes Yes No Yes
Yes Yes No Yes
Yes Yes No Yes
No No No No
Yes Yes No Yes
No No No No
No No No No
No No Yes No
Yes Yes No No
Yes
Yes
Yes
No
Yes
No
No
No
Yes