Functional Description; Block Diagram; Processor; Figure 4-1 Atca-F140 Block Diagram - SMART Embedded Computing ATCA-F140 Series Installation And Use Manual

Functional Description

4.1

Block Diagram

The following block diagram provides a high level functional view of the ATCA-F140 blade
and its interfaces to the front panel, backplane, and RTM.

Figure 4-1 ATCA-F140 Block Diagram

Logical Slot
1 = 1G-KX/BX
40 = 40G-KR4, 4x 10G-KR,
10G-KX4/BX4, 1G-KX/BX
Front
Panel
QSFP+ PPI / 4x SFI
ETH1
QSFP+
PPI / 4x SFI
ETH2
54616S
1G-T
RJ45
PHY
ETH5
RS232
xcvr
RJ45
CONSOLE
DIMM2
DDR3
w/ ECC
SFP+
SFI
ETH3
SFP+
SFI
ETH4
Logical Slot
6x
5x Inter-Shelf Sync
RJ-45
Master/Slave Sync
2x
2x BITS/SSU
RJ-45
4.2

Processor

The ATCA-F140 utilizes an NXP QorIQ P2020 processor. The speed grade used on the
ATCA-F140 is 1.0GHz.
The QorIQ P2020 Integrated Processor provides the following features:
 Dual e500 cores

On-die 32KB L1 cache for each core
 On-die common 512KB L2 cache with ECC

DDR3 memory controller and interface
ATCA-F140 Series Installation and Use (6806800M67S)
3 4 5 6 7 8 9 10 11 12 13 14 15 16
40 40 40 40 40 40 40 40 40 40 40 40 1 1
Backplane Zone 2
Connectors
TopSync Fabric
2x1G-SGMII
12x 40G-KR4
XLAUI / 4x XFI
BCM84740
XLAUI<>PPI
XLAUI / 4x XFI
BCM84740
XLAUI<>PPI
RGMII
54616S
RGMII
1G-SGMII
PHY
x2 PCIe
UART NXP
x1 PCIe SATA
P2020
Bridge
DIMM1 Processor
DDR3
x1 PCIe
w/ ECC
USB
Local Bus
PHY
Boot+Kernel
FileSystem NOR Flash
NAND Flash
Boot+Kernel
NOR Flash
10G-XAUI
BCM8727
2x
10G-XAUI
XAUI<>SFI
12x 1G-SGMII
54680
PHYs
2x 1G-SGMII
Transformers
Backplane Zone 2
Connectors 14x 1G-T
1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 4 5 6 7 8 9 10 11 12 13 14 15 16
25MHz
100MHz PCIE
Clock Distribution
156.25MHz
100MHz
125MHz
5241
54616S
TopSync Fabric PHY PHY
ATCA-F140
4x XFI
WC15
XLAUI / 4x XFI
WC0 WC14
lanes 0-1
Broadcom Fabric=>AMC
WC1-
X-Connect
BCM56846 1G-SGMII
WC0
WC12
lane 2
64x 10G-KR AMC=>Fabric
X-Connect
WC16
+ 4x 1G-KX
1G-SGMII
WC17
82571EB
WC0
PCI-E x4
PCIe lane 3
2x1GbE
1G-SGMII
MAC/PHY
SATA
Port 2
1G-
AMC
SERDES
SATA
Port 1
1G-
HDD
SERDES
Port 0
AMC=>Base
X-Connect
Base=>AMC
X-Connect
PCIe P17
1G-SGMII
P18
HG2
2x 10G-XAUI
HG0-HG1
HG3
1G-SGMII
1G-SGMII
1G-SGMII
P19
Broadcom
4x 1G-SGMII
BCM56334 P20-
P23
24x 1G-KX +
P0-
P11 1G-SGMII
4x 10G-XAUI 1G-T
54616S
P16
PHY
P12-P13
1G-SGMII 10/100-T
P14
1G-SGMII 54680
10/100-T
P15
PHY
2x 1G-SGMII
To Service
Processor
Clock FPGA
10/100-MII
Semtech
SPI to Processor Stratum 3
TopSync
Oscillator
Maxim
Maxim
26503
26503
Framers Framers
Chapter 4
RTM-ATCA-F140
Backplane
FC 1
BCM84754
4x XFI
To Zone 3
4x XFI <>
To Zone 3
Fabric X-Connect:
Tx to UC[4]; Rx to UC[3]
UC[3:4]
Fabric X-Connect:
Tx to UC[3]; Rx to UC[4]
BCM84740
XLAUI <>
XLAUI /
4x XFI
UC[2]
Ports 4-7
To Zone 3
Ports 8-11
Hot
Swap
Control
To Other
Hub
Board
Base X-Connect:
Tx to UC[0]; Rx to UC[1]
BCM8727
UC[0:1]
Base X-Connect:
2x XAUI <>
Tx to UC[1]; Rx to UC[0]
To Zone 3
2x 10G-XAUI
To Zone 3
To Zone 3
To Zone 3 4x 1G-SGMII
BC 2
BC 1[A]
To
ShMCs
BC 1[B]
To Zone 3
Host
Bussed
IPMC
Interface to
IPMB-0
ShMCs/
Blades
FPGA
Bussed
CLK[1:3][A:B]
TCLK
to
Blade
1/2/3
Shaded area indicates circuitry
Slots
for the Telecom Clock feature
SFI
SFP+
ETH6
SFI SFP+
ETH5
SFI
SFI SFP+
ETH4
SFI
SFP+
ETH3
PPI
QSFP+
ETH7
PPI
4x SFI
SFI
SFP+
ETH1
SFI
SFP+
SFI
ETH2
SFP
ETH8
SFP
ETH9
SFP
ETH10
SFP
ETH11
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