Signal Connections For 2-Wire Jtag Communication (Spy-Bi-Wire) - Texas Instruments MSP430 User Manual

Signal Connections for In-System Programming and Debugging
VCC TOOL
VCC TARGET
TEST/VPP
A Make either connection J1 in case a local target power supply is used or connection J2 to power target from the
debug/programming adapter.
B The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access and that any capacitance attached to this signal may affect the ability to establish a connection with the
device. The upper limit for C1 is 2.2 nF when using current TI FET interface modules (USB FET).
C R2 protects the JTAG debug interface TCK signal from the JTAG security fuse blow voltage that is supplied by the
TEST/VPP pin during the fuse blow process. If fuse blow functionality is not needed, R2 is not required (populate
0 ?), and do not connect TEST/VPP to TEST/SBWTCK.
Figure 2-2. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
26
Design Considerations for In-Circuit Programming
V
J1 (see Note A)
J2 (see Note A)
R1
47 k W
(see Note B)
JTAG
TDO/TDI
2 1
4 3
6 5
TCK
8 7
GND
10 9
12 11
14 13
C1
2.2 nF
(see Note B)
© 2009–2010, Texas Instruments Incorporated
CC
C3
C2
0.1 µF
10 µF
R2
330
W
(see Note C)
SLAU278F – May 2009 – Revised December 2010
www.ti.com
V /AV /DV
CC CC CC
MSP430Fxxx
RST/NMI/SBWTDIO
TEST/SBWTCK
V /AV /DV
SS SS SS
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