Page 1 MSP430 Memory Programming User's Guide Literature Number: SLAU265 February 2009...
Page 2 SLAU265 – February 2009 Submit Documentation Feedback...
Page 3: Table Of Contents
MSP430 Programming Via the Bootstrap Loader ........................Introduction ................Standard RESET and BSL Entry Sequence ........2.2.1 MSP430 20-Pin and 28-Pin Flash Devices With Shared JTAG Pins ............2.2.2 MSP430 Flash Devices With Dedicated JTAG Pins ......................UART Protocol ...............
Page 4 Special Consideration for the MSP430F543x BSL ..............Special Consideration for ROM BSL Version 1.10 ......................BSL Known issues ..............Bootstrap Loader PCB Layout Suggestion .............. MSP430 Programming Via the JTAG Interface ........................Introduction ....................Interface and Instructions ................... 8.2.1 JTAG Interface Signals .....................
Page 5 ..............9.6.3 Host Controller/Programmer Power Supply ..............Internal MSP430 JTAG Implementation ..................10.1 TAP Controller State Machine ..........10.2 MSP430 JTAG Restrictions (Non-Compliance With IEEE Std 1149.1) ................Errata and Revision Information SLAU265 – February 2009 Contents Submit Documentation Feedback...
Page 6: List Of Figures
www.ti.com List of Figures ....................Standard RESET Sequence ................BSL Entry Sequence at Shared JTAG Pins ................. BSL Entry Sequence at Dedicated JTAG Pins .................. Bootstrap Loader Interface Schematic ................Universal BSL Interface PCB Layout, Top ................Universal BSL Interface PCB Layout, Bottom ...............
Page 7 Shared JTAG Device Pin Functions ................Erase/Program Minimum TCLK Clock Cycles ................Flash Memory Parameters (f = 450 kHz) ................ 8-10 MSP430 Device JTAG Interface (Shared Pins) ................8-11 MSP430 Device Dedicated JTAG Interface ................8-12 JTAG Features Across Device Families ......................
Page 8 All trademarks are the property of their respective owners. List of Tables SLAU265 – February 2009 Submit Documentation Feedback...
Page 9: Overview Of Msp430 Programming
JTAG programming can be applied to all supported MSP430 families. BSL programming on the MSP430 can be broken into two primary methods: using the ROM-based BSL of the 1xx, 2xx, and 4xx families, and using the flash-based BSL of the 5xx family. While each methods has its own protocol and thus separate chapter, the hardware and reset sequences are common across all devices.
Page 10 Overview of MSP430 Programming SLAU265 – February 2009 Submit Documentation Feedback...
Page 11: Msp430 Programming Via The Bootstrap Loader
If the device is secured by disabling JTAG, it is still possible to use the BSL. Access to the MSP430 memory via the BSL is protected against misuse by a user-defined password.
Page 12: Standard Reset And Bsl Entry Sequence
2.2.1 MSP430 20-Pin and 28-Pin Flash Devices With Shared JTAG Pins Applying an appropriate entry sequence on the RST/NMI and TEST pins forces the MSP430 to start program execution at the BSL RESET vector instead of at the RESET vector located at address FFFEh.
Page 13: Msp430 Flash Devices With Dedicated Jtag Pins
UART Protocol www.ti.com 2.2.2 MSP430 Flash Devices With Dedicated JTAG Pins Devices with dedicated JTAG pins use the TCK pin instead of the TEST pin. The BSL program execution starts whenever the TCK pin has received a minimum of two negative...
Page 14 MSP430 Programming Via the Bootstrap Loader SLAU265 – February 2009 Submit Documentation Feedback...
Page 15: Rom-Based Bootstrap Loader Protocol
Chapter 3 SLAU265 – February 2009 ROM-Based Bootstrap Loader Protocol Synchronization Sequence Before sending any command to the BSL, a synchronization character (SYNC) with its value of 80h must be sent to the BSL. This character is necessary to calculate all the essential internal parameters, which maintain UART and flash memory program/erase timings.
Page 16: Programming Flow
Programming Flow www.ti.com Programming Flow The write access (RX data block command) to the flash memory/RAM or peripheral modules area is executed online. That means a data byte/word is processed immediately after receipt and the write cycle is finished before a following byte/word has completely arrived. Therefore, the entire write time is determined by the baud rate, and no buffering mechanism is necessary.
Page 17: Data Frame
Data Frame www.ti.com Data Frame To ensure high data security during the data transmission, a data frame protocol called serial standard protocol (SSP) is used. The BSL is considered the receiver in Table 3-1. 3.4.1 Data-Stream Structure • The first eight bytes (HDR through LH) are mandatory (xx represents dummy data). •...
Page 18: Checksum
CKH = INV [ B2 XOR B4 XOR … XOR Bn ] 3.4.3 Example Sequence The following example shows a request to read the memory of the MSP430 from location 0x0F00. All values shown below are represented in hexadecimal format.
Page 19 DATA_ACK is sent back by the BSL. Otherwise, the BSL confirms with a DATA_NAK. Note: BSL versions V1.40 and higher support online verification inside the MSP430 for addresses 0200h to FFFFh, which reduces programming/verification time to 50%. Online verification means that the data is immediately verified with the data that is written into the flash without transmitting it again.
Page 20 Data Frame www.ti.com Erase segment 0 clears the password area and, therefore, the remaining password is 32 times 0FFh. When applying LL = 0x04 and LH = 0xA5, a mass erasure of only the main memory is performed. Indeed, this command must be executed a minimum of 12 times to achieve a total erasure time of >200 ms. No subsequent erase check of the entire main memory is done.
Page 21: Recommendations For Msp430F149 ['F449]
Data Frame www.ti.com Note: The highest achievable baud rate depends on various system and environment parameters like supply voltage, temperature range, and minimum/maximum processor frequency. See the corresponding device specification/data sheet. Note: This command is implemented on BSL versions V1.60 or higher or available in the loadable bootstrap loader BL_150S_14x.txt.
Page 22: Loadable Bsl
Loadable BSL www.ti.com 3.4.4.11 TX Data Block The transmit data block command is used for any read access to the flash memory/RAM or peripheral module control registers at 0000h to 01FFh. It is password protected. The 16-bit block start address is defined in AL (low byte) and AH (high byte). The 16-bit block length is defined in LL (low byte) and LH (high byte).
Page 23: Exiting The Bsl
LOCKA bit should also be checked. • Applying the standard RESET sequence (see Figure 2-1) forces the MSP430 to start with the user reset vector at address 0FFFEh. Password Protection The password protection prohibits every command that potentially allows direct or indirect data access.
Page 24: Bsl Internal Settings And Resources
• 0FF0h to 0FF1h: Chip identification (e.g., F413h for an F41x device). • 0FFAh to 0FFBh: BSL version number (e.g., 0130h for BSL version V1.30). Please see the MSP430 device/BSL version assignment in Chapter 3.9.2 Vectors to Call the BSL Externally The entry part of the boot ROM holds the calling vectors for BSL access by program: •...
Page 25: Memory Allocation And Resources
BSL Internal Settings and Resources www.ti.com • SW-UART: Timer_A operates in continuous mode with MCLK source (Div = 1) CCR0 used for compare CCTL0 used for polling of CCIFG0 • TX pin is set to output HI for RS232 idle state •...
Page 26 ROM-Based Bootstrap Loader Protocol SLAU265 – February 2009 Submit Documentation Feedback...
Page 27: Flash-Based Bootstrap Loader Protocol
Chapter 4 SLAU265 – February 2009 Flash-Based Bootstrap Loader Protocol BSL Data Packet The BSL data packet has a layered structure. The BSL core command contains the actual command data to be processed by the BSL. In addition the standard BSL commands, there can be wrapper data before and after each core command known as the peripheral interface code (PI Code).
Page 28: Messages
Timer_A UART Peripheral Interface (PI) www.ti.com 4.2.3 Messages The peripheral interface section of the BSL430 software parses the wrapper section of the BSL data packet. If there are errors with the data transmission, an error message is sent immediately. An ACK is sent after all data has been successfully received and does not mean that the command has been correctly executed (or even that the command was valid) but, rather, that the data packet was formatted correctly and passed on to the BSL core software for interpretation.
Page 29: Bsl Core Command Structure
BSL Core Command Structure www.ti.com BSL Core Command Structure The BSL core command is transmitted in the format shown in Table 4-3. All numbers are in hexadecimal format. Note: Section 6.1 for using the following commands with the BSL in the MSP430F5438 (non-A version).
Page 30: Bsl Security
All the flash in the MSP430 is erased. This function unlocks and erases information memory A. CRC Check The MSP430 performs a 16-bit CRC check using the CCITT standard. The address given is the first byte of the CRC check. Two bytes are used for the length.
Page 31: Bsl Core Responses
BSL Core Responses www.ti.com BSL Core Responses The BSL core responses are always wrapped in a peripheral interface wrapper with the identical format to that of received commands. The BSL core can respond in the format shown in Table 4-4. All numbers are in hexadecimal format.
Page 32: Bsl Version Number
The version number for the section of code that interprets BSL core commands. Byte 3: API Version The version number for the section of code that reads and writes to MSP430 memory. Byte 4: Peripheral Interface Version The version number for the section of code that manages UART communication.
Page 33: Bootstrap Loader Hardware
Bootstrap Loader Hardware This chapter describes simple and low-cost hardware and software solutions to access the bootstrap loader functions of the MSP430 flash devices via the serial port (RS-232) of a PC Hardware Description The low-cost hardware presented in this document (see...
Page 34: Serial Interface
Hardware Description www.ti.com 5.1.2 Serial Interface Table 5-1 shows the signals used to communicate with the bootstrap loader (via connector J2). The names reflect the pin function as seen from the PC. For example, the PC receives data via the RxD pin, whereas the bootstrap loader needs to drive this signal.
Page 35: Target Connector
Control of RST/NMI and TEST or TCK Pins The two pins used to invoke the bootstrap loader software of the MSP430—RST/NMI and TEST or TCK (for devices without a dedicated TEST pin)—are controlled via the DTR and RTS signals, respectively.
Page 36: Parts List
Hardware Description www.ti.com 5.1.4 Parts List Table 5-4. Universal BSL Interface Parts List PART VALUE/PART NUMBER PACKAGE COMMENT 33 µF, 16 V SMD 7243 100 nF SMD 0805 2.2 µF, 6.3 V SMD 1206 100 nF SMD 0805 33 µF, 16 V SMD 7243 100 nF SMD 0805...
Page 37: Differences Between Devices And Bootstrap Loader Versions
Chapter 6 SLAU265 – February 2009 Differences Between Devices and Bootstrap Loader Versions Special Consideration for the MSP430F543x BSL The following special notes apply to the MSP430F543x BSL. • The '543x BSL does not contain a mechanism to unlock the BSL area for erasing and writing a custom BSL.
Page 38: Bsl Known Issues
BSL Known issues www.ti.com BSL Known issues BSL Command Erase Main or Info Versions Affected Description Does not erase information memory when supplied with address in info memory Workarounds Use Erase Segment Command BSL Command Erase Main or Info Versions Affected Reports failure when first segment of code memory is supplied as address.
Page 39: Bsl Version 1.10 On F13X, F14X(1), F11X, And F11X1
BSL Known issues www.ti.com In summary, the tables in this chapter show the key information of MSP430 device/BSL version assignment related to their hard/software resources. Table 6-1. BSL Version 1.10 on F13x, F14x(1), F11x, and F11x1 F13x F11x (obsolete) Device...
Page 40: Bsl Version 1.30 On F41X, F11X, And F11X1
BSL Known issues www.ti.com Table 6-2. BSL Version 1.30 on F41x, F11x, and F11x1 F11x (obsolete) Device F14x F11x1A BSL Version 1.30 Cold start 0C00h BSL vector address Warm start 0C02h Chip ID address 0FF0h Chip ID data F143h F112h BSL version address 0FFAh BSL version data...
Page 41: Bsl Version 1.40 On F12X
BSL Known issues www.ti.com Table 6-3. BSL Version 1.40 on F12x Device F122, F123x BSL Version 1.40 Cold start 0C00h BSL vector address Warm start 0C02h Chip ID address 0FF0h Chip ID data F123h BSL version address 0FFAh BSL version data 0140h Mass erase time, nominal (ms) 206.4...
Page 42: Bsl Version 1.60 On F11X2, F12X2, F43X, F44X, Fe42X, Fw42X, Fg43X
BSL Known issues www.ti.com Table 6-4. BSL Version 1.60 on F11x2, F12x2, F43x, F44x, FE42x, FW42x, FG43x, F415, F417 FE42x, F1122, F1222, F43x, FW42x, Device FG43x F1132 F1232 F44x F415, F417 BSL Version 1.60 Cold start 0C00h BSL vector address Warm start 0C02h Chip ID address...
Page 43: Bsl Version 1.61 On F16X, F161X, F42X0, F149 Rev Aa (And Later)
BSL Known issues www.ti.com Table 6-5. BSL Version 1.61 on F16x, F161x, F42x0, F149 rev AA (and later) Device F16x F161x F149 Rev AA F42x0 BSL Version 1.61 Cold start 0C00h BSL vector address Warm start 0C02h Chip ID address 0FF0h Chip ID data 0F169h...
Page 44: Bsl Version 2.02 On F21Xx, F22Xx, F24X, F23X
BSL Known issues www.ti.com Table 6-6. BSL Version 2.02 on F21xx, F22xx, F24x, F23x Device F21x1 F22xx F24x BSL Version 2.02 Cold start 0C00h BSL vector address Warm start 0C02h Chip ID address 0FF0h Chip ID data F213h F227h F249h BSL version address 0FFAh BSL version data...
Page 45: Bsl Version 2.12/2.13 On Fg46Xx, F261X, F471Xx
BSL Known issues www.ti.com Table 6-7. BSL Version 2.12/2.13 on FG46xx, F261x, F471xx Device FG46xx F471xx F261x BSL Version 2.12 2.13 2.13 Cold start 0C00h BSL vector address Warm start 0C02h Chip ID address 0FF0h Chip ID data F46Fh F26Fh BSL version address 0FFAh BSL version data...
Page 46 Differences Between Devices and Bootstrap Loader Versions SLAU265 – February 2009 Submit Documentation Feedback...
Page 47: Bootstrap Loader Pcb Layout Suggestion
Chapter 7 SLAU265 – February 2009 Bootstrap Loader PCB Layout Suggestion unitop.wmf@ Figure 7-1. Universal BSL Interface PCB Layout, Top unibottom.wmf@ Figure 7-2. Universal BSL Interface PCB Layout, Bottom SLAU265 – February 2009 Bootstrap Loader PCB Layout Suggestion Submit Documentation Feedback...
Page 48: Universal Bsl Interface Component Placement
www.ti.com 3,5 mm Figure 7-3. Universal BSL Interface Component Placement Bootstrap Loader PCB Layout Suggestion SLAU265 – February 2009 Submit Documentation Feedback...
Page 49: Universal Bsl Interface Component Placement
www.ti.com 3,5 mm Figure 7-4. Universal BSL Interface Component Placement SLAU265 – February 2009 Bootstrap Loader PCB Layout Suggestion Submit Documentation Feedback...
Page 50 Bootstrap Loader PCB Layout Suggestion SLAU265 – February 2009 Submit Documentation Feedback...
Page 51: Msp430 Programming Via The Jtag Interface
MSP430 flash-based microcontroller family using the JTAG communication port. In addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices. Device access using standard 4-wire JTAG and 2-wire JTAG [also referred to as Spy-Bi-Wire (SBW)] is discussed.
Page 52: Interface And Instructions
MSP430 devices. All devices support the JTAG 4-wire interface. In addition, some devices also support the next-generation optimized 2-wire JTAG (Spy-Bi-Wire) interface. Using these signals, an interface connection to access the MSP430 JTAG port using a PC or other controller can be established. See the section Signal Connections for In-System Programming and Debugging, MSP-FET430PIF, MSP-FET430UIF, GANG430, PRGS430 in the MSP-FET430 Flash Emulation Tool (FET) (For Use With CCE v2.0) User's Guide (SLAU157) or the MSP-FET430 Flash Emulation Tool (FET) (For Use With IAR...
Page 53: Spy-Bi-Wire Basic Concept
In order to reduce the overhead of the 2-wire interface, the SBWTDIO line is shared with the RST/NMI pin of the MSP430. Table 8-2 gives a general overview of MSP430 devices and their respective JTAG interface implementation. Table 8-2. JTAG Signal Implementation Overview...
Page 54: Jtag Access Macros
This macro loads a desired JTAG instruction into the JTAG instruction register (IR) of the target device. In the MSP430, this register is eight bits wide with the least significant bit (LSB) shifted in first. The data output from TDO during a write to the JTAG instruction register contains the version identifier of the JTAG interface (or JTAG ID) implemented on the target device.
Page 55: Data Register I/O: Dr_Shift16 (0X158B) (Tdo Output Is 0X55Aa)
8.2.2.1.2 DR_SHIFT16 (16-bit Data) This macro loads a 16-bit word into the JTAG data register (DR). (In the MSP430, a data register is 16 bits wide.) The data word is shifted, most significant bit (MSB) first, into the target MSP430’s TDI input.
Page 56: Address Register I/O: Dr_Shift20 (0X12568) (Tdo Output Is 0Xa55Aa)
8.2.2.1.4 MsDelay (time) This macro causes the programming interface software to wait for a specified amount of time in milliseconds (ms). While this macro is executing, all signals to and from the target MSP430 must hold their previous values. 8.2.2.1.5 SetTCLK This macro sets the TCLK input clock (provided on the TDI signal input) high.
Page 57: Spy-Bi-Wire (Sbw) Timing And Control
The following sections provide a basic understanding of the SBW implementation as it relates to supporting generation of the macro function timing signals. This is intended to enable development of custom MSP430 programming solutions, rather than just relying on the example application code also provided.
Page 58: Sbw-To-Jtag Interface Diagram
SBW logic is deactivated and must be activated again according to Section 8.3.1. When using the provided source code example, make sure that interrupts are disabled during the SBWTCK low phase to ensure accurate timings. MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 59: Detailed Sbw Timing Diagram
MASTER SLAVE SBWTDIO SBWTCK TMS_SLOT TDI_SLOT TDO_SLOT TMS_SLOT TDI_SLOT TDO_SLOT SHIFT_COUNT LOAD_JTAG_REG JTAG_REG TCLK JTAG TAP TAP STATE TAP STATE STATE Figure 8-9. Detailed SBW Timing Diagram SLAU265 – February 2009 MSP430 Programming Via the JTAG Interface Submit Documentation Feedback...
Page 60: Synchronization Of Tdi/Tclk During Run-Test/Idle
Latched at 0 TDI/TCLK during previous (internal signal) TDI Slot Case 2b: Latched at 1 TDI/TCLK during previous (internal signal) TDI Slot Figure 8-10. Synchronization of TDI/TCLK During Run-Test/Idle MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 61: Jtag Communication Instructions
Section 8.2.2.1.1. The following instructions that can be written to the JTAG IR are used to program the target flash memory. All instructions sent to the target MSP430 via the JTAG register are transferred LSB first. Table 8-4. Memory Access Instructions...
Page 62 JTAG MDB register. As the new value is written into the MDB register, the prior value in the MSP430 MDB is captured and shifted out on TDO. The MSP430 MAB is set by the value in the JTAG MAB register during execution of the IR_DATA_TO_ADDR instruction.
Page 63: Jtag Control Signal Register For 1Xx/2Xx/4Xx Families
MSP430’s JTAG control module. 8.2.4.3 Controlling the CPU The following instructions enable control of the MSP430 CPU through a 16-bit register accessed via JTAG. This data register is called the JTAG control signal register. Table 8-5 describes the bit functions making up the JTAG control signal register used for memory access.
Page 64: Jtag Control Signal Register For 5Xx Family
Simultaneously, the last value stored in the register is shifted out on TDO. The new value takes effect when the TAP controller enters the UPDATE-DR state. MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 65 This instruction completely releases the CPU from JTAG control. Once executed, the JTAG control signal register and other JTAG data registers no longer have any effect on the target MSP430 CPU. This instruction is normally used to release the CPU from JTAG control.
Page 66: Memory Programming Control Sequences
• MSP430 devices with TEST pin and 4-wire JTAG access only (no SBW) To use the JTAG features of MSP430 devices with shared JTAG and a TEST pin, it is necessary to enable the shared JTAG pins for JTAG communication mode. (Devices with dedicated JTAG inputs/outputs and no TEST pin do not require this step.) The shared pins are enabled for JTAG...
Page 67: Jtag Access Entry Sequences (For Devices Supporting Sbw)
Figure 8-11. JTAG Access Entry Sequences (for Devices Supporting SBW) Note: On some Spy-Bi-Wire capable MSP430 devices the TEST/SBWTCK is very sensitive to rising signal edges which could cause the test logic to enter a state where according entry sequences (either 2-wire or 4-wire) are not recognized correctly and JTAG access stays disabled.
Page 68: Fuse Check And Tap Controller Reset
Fuse Check and Reset of the JTAG State Machine (TAP Controller) Reference functions: ResetTAP, ResetTAP_sbw Each MSP430 family device includes a physical fuse used to permanently disable memory access via JTAG communication. When this fuse is programmed (or blown), access to memory via JTAG is permanently disabled and cannot be restored.
Page 69: General Device (Cpu) Control Functions
Memory Programming Control Sequences www.ti.com 8.3.2 General Device (CPU) Control Functions The functions described in this section are used for general control of the target MSP430 CPU, as well as high-level JTAG access and bus control. 8.3.2.1 Function Reference for 1xx/2xx/4xx Families 8.3.2.1.1 Taking the CPU Under JTAG Control...
Page 70 8.3.2.1.3 Setting the Target CPU Program Counter (PC) In order to use some of the features of the JTAG interface provided by the MSP430, setting of the CPU PC of the target device is required. The following flow is used to accomplish this. Implementations for both the MSP430 and MSP430X architectures are shown.
Page 71 The CPU is now in the instruction-fetch state and ready to receive a new JTAG instruction. If the PC has been changed while the memory was being accessed, the PC must be loaded with the correct address. SLAU265 – February 2009 MSP430 Programming Via the JTAG Interface Submit Documentation Feedback...
Page 72 DR_SHIFT16(0x5A80) : Write to Watchdog Control Register SetTCLK The target CPU is now released for the next operation. ClrTCLK IR_SHIFT("IR_CNTRL_SIG_16BIT") DR_SHIFT16(0x2401) : Set to Read IR_SHIFT("IR_ADDR_CAPTURE") SetTCLK MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 73 0xFFFEh (the reset vector). • Release MSP430 from JTAG control. This is done by performing a reset using the JTAG control signal register. The CPU must then be released from JTAG control by using the IR_CNTRL_SIG_RELEASE instruction.
Page 74 JTAG Control Signal Register. Also care must be taken that the CPU is in the so called Full-Emulation-State (equivalent to the Instruction-Fetch state for MSP430/MSP430X architectures) by setting the CPUSUSP signal and providing a number of TCLK until the CPU pre-fetch pipes are cleared.
Page 75 DR_SHIFT16("PC_Value") : Insert the lower 16 bit value for PC ClrTCLK SetTCLK DR_SHIFT16(0x4303) : insert NOP instruction to be pre-fetched by CPU ClrTCLK : Now PC is set IR_SHIFT("IR_ADDR_CAPTURE") DR_SHIFT20(0x00000) Load PC completed SLAU265 – February 2009 MSP430 Programming Via the JTAG Interface Submit Documentation Feedback...
Page 76 JTAG control starts execution of the previously programmed user code, which might change the flash memory content. In that case, verification of the memory content against the originally programmed code image would fail. MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 77: Accessing Non-Flash Memory Locations With Jtag
To read from any memory address location (peripherals, RAM, or flash), the R/W signal must be set to READ using the JTAG control signal register (bit 0 set to 1). The MSP430 MAB must be set to the specific address to be read using the IR_ADDR_16BIT instruction while TCLK is 0. To capture the corresponding value of the MSP430 MDB, the IR_DATA_TO_ADDR instruction must be executed.
Page 78 MAB and MDB. After completion of the write operation, it is recommended to set the R/W signal back to READ. Following is the flow for a peripheral or RAM memory address write. Implementations for both the MSP430 and MSP430X architectures are shown.
Page 79 Before this instruction can be loaded into the JTAG IR register, the program counter (PC) of the target MSP430 CPU must be set to the desired memory starting address. After the IR_DATA_QUICK instruction is shifted into the IR register, the PC is incremented by two with each falling edge of TCLK, automatically pointing the PC to the next memory location.
Page 80 Memory Programming Control Sequences www.ti.com 8.3.3.3.1 Flow for Quick Read (All Memory Locations) • Both MSP430 and MSP430X architecture, Reference function: ReadMemQuick Set PC to start address – 4 (SetPC resp. SetPC_430X) Switch CPU to stopped state (HaltCPU) ClrTCLK IR_SHIFT("IR_CNTRL_SIG_16BIT")
Page 81: Programming The Flash Memory (Using The Onboard Flash Controller)
Function Reference for 1xx/2xx/4xx Families Reference function: WriteFLASH This section describes one method available to program the flash memory module in an MSP430 device. It uses the same procedure that user-defined application software would utilize, which would be programmed into a production-equipment MSP430 device. Note that nonconsecutive flash memory addressing is supported.
Page 82 Memory Programming Control Sequences www.ti.com The following JTAG communication flow shows programming of the MSP430 flash memory using the onboard flash controller. In this implementation, 16-bit words are programmed into the main flash memory area. To program bytes, the BYTE bit in the JTAG CNTRL_SIG register must be set high while in programming mode.
Page 83 Having its own dedicated Timing Generator available on chip, Flash access with the 5xx family becomes significantly easier compared to the other MSP430 families. One need not take care about providing a certain erase/program frequency via the TCLK signal. All timings, required for both Flash memory erase- and write-access, are generated automatically.
Page 84: Accessing Flash Memory
The provided source code example includes a Flash-Write-Code example that has the capability to be parameterized in binary state. Figure 8-14 shows a generic map of the binary image of the Flash-Access-Code(s) provided with this document. MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 85: Flash Access Code Binary Image Map
Provide TCLK cycles for Flash-Write-Code processing (at least 30 cycles in a minimum time of t MAX (see the device-specific data sheet)) Word Write Another Flash Address? Get target device in Full-Emulation-State SLAU265 – February 2009 MSP430 Programming Via the JTAG Interface Submit Documentation Feedback...
Page 86: Erasing The Flash Memory (Using The Onboard Flash Controller)
IR_SHIFT("IR_DATA_TO_ADDR") DR_SHIFT16(0xA540) : Source is MCLK, divider by 1 SetTCLK ClrTCLK IR_SHIFT("IR_ADDR_16BIT") DR_SHIFT16(0x012C) : Point to FCTL3 Address Replace with DR_SHIFT20("Address") when programming an MSP430X architecture device. MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 87 The EraseAddr parameter is the address pointing to the flash memory segment to be erased. Correct timing required. Must meet min/max TCLK frequency requirement of 350 kHz ±100 kHz. SLAU265 – February 2009 MSP430 Programming Via the JTAG Interface Submit Documentation Feedback...
Page 88: Flash Memory Parameters
For implementation 1, in order to assure the recommended 200-ms erase time to safely erase the flash memory space, 5300 TCLK cycles are transmitted to the target MSP430 device and repeated 19 times. With implementation 2, the following sequence needs to be performed only once.
Page 89 The Flash-Erase-Code can be executed either under JTAG control or in free-running mode. Similar to what is described in Section 8.3.4.2 the JTAG mailbox system is used to retrieve the current execution state of the Flash-Erase-Code in the target device. SLAU265 – February 2009 MSP430 Programming Via the JTAG Interface Submit Documentation Feedback...
Page 90: Reading From Flash Memory
8.4.1 Burning the JTAG Fuse - Function Reference for 1xx/2xx/4xx Families Two similar methods are described and implemented, depending on the target MSP430 device family. All devices having a TEST pin use this input to apply the programming voltage, V .
Page 91 Switch TDI pin back to TDI function and reset the JTAG state machine (ResetTAP) 8.4.1.1.2 Fuse-Programming Voltage Via TEST Pin The same method is used to program the fuse for the TEST pin MSP430 devices, with the exception that the fuse-blow voltage, V , is now applied to the TEST input pin.
Page 92: Programming The Jtag Lock Key - Function Reference For 5Xx Family
(BSL) memory at addresses 0x17FC to 0x17FF. Anything other than 0 or 0xFFFFFFFF programmed to these addresses locks the JTAG interface irreversibly. All of the 5xx MSP430 devices come with a preprogrammed BSL (TI-BSL) code which by default protects itself from unintended erase and write access.
Page 93: Testing For A Successfully Protected Device
RESET (via the JTAG ExecutePOR command or the RST/NMI pin in hardware) has been issued, the only JTAG function available on the target MSP430 is BYPASS. When the target is in BYPASS, data sent from host to target is delayed by one TCK pulse and output on TDO, where it can be received by other devices downstream of the target MSP430.
Page 94 Length (number of words within the data block) word *DataArray (pointer to an array containing the data, 0 for erase check) Result: word (STATUS_OK if comparison was successful, STATUS_ERROR otherwise) MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 95: High-Level Jtag Routines
JTAG Function Prototypes www.ti.com 8.5.2 High-Level JTAG Routines word GetDevice (void) Takes the target MSP430 device under JTAG control. Sets the target device’s CPU watchdog to a hold state; sets the global DEVICE variable. Arguments: None Result: word (STATUS_ERROR if fuse is blown, JTAG_ID is incorrect (not = 0x89) or synchronizing time-out occurs;...
Page 96 StartAddr (start address of memory to be checked) word Length (number of words to be checked) Result: word (STATUS_OK if erase check was successful, STATUS_ERROR otherwise) MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 97 (STATUS_OK if fuse blow was successful, STATUS_ERROR otherwise) word IsFuseBlown (void) Determines if the security fuse has been programmed on the target device Arguments: None Result: word (STATUS_OK if fuse is blown, STATUS_ERROR otherwise) SLAU265 – February 2009 MSP430 Programming Via the JTAG Interface Submit Documentation Feedback...
Page 98: Jtag Features Across Device Families
FALSE the CPU of the device still works in the background while the PSA checksum algorithm is executed. This fact requires a POR being performed after checksum calculation. With the enhanced PSA hardware implementation the CPU is completely halted during checksum calculation. A POR is not required afterwards. MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 99: References
Third-Party Support SoftBaugh, Inc., offers a complete system as shown in Chapter 9, which is compatible with the software available with the MSP430 Flash Programming Replicator application report. This information can be found at this address: http://www.softbaugh.com/ExtREP430.html SoftBaugh, Inc. 5400 Laurel Springs Parkway...
Page 100 MSP430 Programming Via the JTAG Interface SLAU265 – February 2009 Submit Documentation Feedback...
Page 101: Jtag Programming Hardware And Software Implementation
(http://www.ti.com/lit/zip/slau265). Each example demonstrates the software functions described in the previous sections using an MSP430F149 as the host controller that programs the given target MSP430 flash-based device of choice. The complete C source code and project files are provided in the attachment accompanying this user's guide.
Page 102: Software Operation
(61 KB available on the MSP430F149). The programming software itself occupies about 3.5 KB, so approximately 57 KB remain for the target device program. The Replicator host can be loaded with the target source code via the flash emulation tool (FET) or the MSP430 serial programming adapter. (See the MSP430 website at www.ti.com...
Page 103: Software Structure
Target_Code.s43 (IAR) resp. Target_Code.asm (CCE) from the project. The Target_Code.h file is generated by the srec_cat.exe file directly or via the srec.bat file. JTAG functions All MSP430-specific functions are defined here. These files should not be modified under any circumstance. JTAGfunc.c JTAGfuncSBW.c Contain the MSP430-specific functions needed for flash programming JTAGfunc430X.c...
Page 104 To enable easy porting of the software to other microcontrollers, the provided source code is written in ANSI-C. As always, it is recommended that the latest available version of the applicable MSP430 development software be installed before beginning a new project. JTAG Programming Hardware and Software Implementation SLAU265 –...
Page 105: Programmer Operation
The target MSP430 device is connected to the host controller/programmer through the 14-pin connector labeled Target JTAG, which has the same standard signal assignment as all available MSP430 tools (FET and PRGS tools). The host supply voltage of 3.6 V is also available on pin 2 of this connector, eliminating the need for an additional supply for the target system, but it does not have to be used at the target.
Page 106: Replicator Application Schematic
Hardware Setup www.ti.com Figure 9-1. Replicator Application Schematic JTAG Programming Hardware and Software Implementation SLAU265 – February 2009 Submit Documentation Feedback...
Page 107 Note: An MSP430 flash programmer system designed for a specific MSP430 target device or a system not implementing fuse-blow functionality may require fewer relays or no relays at all. The programmer system described herein was developed with the intention that it can be used with any MSP430 flash-based device, across all families, including all memory access functionality, as well as fuse-blow capability.
Page 108 JTAG Programming Hardware and Software Implementation SLAU265 – February 2009 Submit Documentation Feedback...
Page 109: Tap Controller State Machine
Figure 10-1. TAP Controller State Machine 10.2 MSP430 JTAG Restrictions (Non-Compliance With IEEE Std 1149.1) • The MSP430 device must be the first device in the JTAG chain (because of clocking via TDI and JTAG fuse check sequence). • Only the BYPASS instruction is supported. There is no support for SAMPLE, PRELOAD, or EXTEST instructions.
Page 110 Internal MSP430 JTAG Implementation SLAU265 – February 2009 Submit Documentation Feedback...
Page 111: Revision History
• Appendix D: Universal Bootstrap Loader Interface Board: Operational amplifier IC2 must be replaced with TL062D or equivalent type. The following is a summary of changes in former revisions of the Programming a Flash-Based MSP430 Using the JTAG Interface application report (SLAA149).
Page 112 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

Texas Instruments MSP430 User Manual

1 Overview of MSP430 Programming

2 MSP430 Programming Via the Bootstrap Loader

3 ROM-Based Bootstrap Loader Protocol

4 Flash-Based Bootstrap Loader Protocol

5 Bootstrap Loader Hardware

6 Differences between Devices and Bootstrap Loader Versions

7 Bootstrap Loader PCB Layout Suggestion

8 MSP430 Programming Via the JTAG Interface

9 JTAG Programming Hardware and Software Implementation

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