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2.11.2 BIOS Boot Selection
For COM.0 R3, the Module Carrier based BIOS options have been expanded to support eSPI devices. A
third pin that affects the BIOS location, named ESPI_EN#, works in conjunction with BIOS_DIS1# and
BIOS_DIS0# to define the BIOS boot path. Additionally, the concepts of Master Attached Flash Sharing
(MAFS) and Slave Attached Flash Sharing (SAFS) are introduced.
LPC bus BIOS FWH support is removed in COM.0 R3. SPI and eSPI BIOS options are supported.
SPI Boot Flash Background
Contemporary Intel x86 systems requires that the SPI boot flash to be divided into a number of regions
that may include:
Descriptor
BIOS code
Management Engine (ME) code
GBE parameters
Platform data
The Descriptor defines where the other regions are in the SPI device(s). The Descriptor is always at the
bottom of the first SPI device, the SPI device that is selected by chipset SPI0 chip-select (chipset
SPI_CS0#).
The first two regions, the Descriptor and the BIOS, are mandatory. The other regions are optional. The
regions may all be packed into the same SPI device, or may be divided between more than one SPI
device, although the Descriptor has to be at the bottom of the first SPI device. In most situations, all the
SPI regions are packed into a single SPI device that is either on the Module or on the Carrier. Designers
may have reasons for dividing the SPI boot flash regions between devices.
COM Express Rev 2 and Rev 3 define a SPI interface on the COM Express connector. The COM
Express SPI interface has only one chip select. Chipsets typically have 2 SPI chip selects. Module
hardware may steer those chipset chip selects to an on-Module SPI device or devices or to a single
off-module SPI device. The chip select steering is defined by the ESPI_EN#, BIOS_DIS1# and
BIOS_DIS0# signals.'BIOS Selection Straps' below.
may
The BIOS Entry point
may
The Module
have one or two SPI devices. Carrier Boards
be in SPI0 or SPI1 as determined by the descriptor table in the SPI0 device.
９５
may
have zero or one SPI devices.
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