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SPI Power
Introducing a SPI_POWER pin is desirable because some Module implementations will have the SPI
power domain in power state S0 and others in S5. It is easier for Carrier Board designers to take the
Carrier SPI power from a pin on the Module.
The SPI_POWER voltage level was defined as 3.3V in COM.0 Rev. 2. With COM.0 Rev. 3, the
may
SPI_POWER voltage level
be 3.3V or 1.8V. This allows the Carrier SPI interface to operate at the
level appropriate for the Module chipset, without the use of level shifters.
should
Module designs that implement a 1.8V Carrier SPI interface
protect themselves against possible
exposure to 3.3V Carrier SPI signals.
should
Carrier designs that implement a 1.8V SPI interface
protect themselves against possible
exposure to 3.3V Module SPI signals.
Module Vs Carrier Board Pull-ups
shall
There
not be any Carrier Board pull-ups or pull-downs on the five SPI_x signals. All such
shall
shall
terminations
be on the Module. The Module designer
determine the correct power domain that
these signals are terminated to.
shall
Note: Carrier Board
implement pull-ups to SPI_POWER on the SPI flash pins HOLD# and WP#
which are not supported on the COM Express connector.
９４
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