Advantech SOM-5992 Design Manual page 51

Signal
10G_PHY_CAP_23
10G_SFP_SDA0
10G_SFP_SCL0
10G_SFP_SDA1
10G_SFP_SCL1
Pin# Description
PHY mode capability pin: Indicates if the PHY
D34
for 10G lanes 2 and 3 is capable of
configuration by I2C. High indicates MDIO-only
configuration, and low indicates configuration
capability via I2C or MDIO. The actual protocol
used for PHY configuration is determined by
the module, in part based on
this input. The actual protocol used is indicated
over the dedicated I2C interface (see Table 13)
Carrier board:
C39 I2C data signal of the 2-wire management
interface used by the 10GbE controller to
access the management registers of an
external Optical SFP Module.
Carrier board:
D39 I2C clock signal of the 2-wire management
interface used by the 10GbE controller to
access the management registers of an
external Optical SFP Module.
Carrier board:
C38 I2C data signal of the 2-wire management
interface used by the 10GbE controller to
access the management registers of an
external Optical SFP Module.
Carrier board:
D38 I2C clock signal of the 2-wire management
interface used by the 10GbE controller to
access the management registers of an
external Optical SFP Module.
Carrier board:
４９
I/O Notes
1
I CMOS
3.3V
Suspend
/
3.3V
I/O OD
CMOS
3.3V
Suspend
/
3.3V
I/O OD
CMOS
3.3V
Suspend
/
3.3V
I/O OD
CMOS
3.3V
Suspend
/
3.3V
I/O OD
CMOS
3.3V
Suspend
/
3.3V