Advantech SOM-5992 Design Manual page 89

Signal Pin#
LPC_FRAME# B3
ESPI_CS0#
LPC_AD0 B4
LPC_AD1 B5
LPC_AD2 B6
LPC_AD3 B7
ESPI_IO_0
ESPI_IO_1
ESPI_IO_2
ESPI_IO_3
LPC_DRQ0# B8
LPC_DRQ1# B9
ESPI_ALERT0#
ESPI_ALERT1#
Description
LPC frame indicates start of a new cycle or
termination of a broken cycle.
Carrier Board:
LPC - LFRAME#
N/C if not used
ESPI Mode: eSPI Master Chip Select Outputs
Driving Chip Select0#. A low selects a particular
eSPI slave for the transaction. Each of the eSPI
slaves is connected to a dedicated Chip Selectn#
pin.
Carrier Board:
Connect to
eSPI Device – eSPI_CS0#
N/C if not used
LPC multiplexed command, address and data.
Carrier Board:
Connect to
LPC - LAD0 , LAD1, LAD2, LAD3
N/C if not used
ESPI Mode: eSPI Master Data Input / Outputs
These are bi-directional input/output pins used to
transfer data between master and slaves.
Multiplexed with LPC_AD[0:3]
Carrier Board:
Connect to
eSPI Device – eSPI_IO0, eSPI_IO1, eSPI_IO2,
eSPI_IO3, the Carrier shall have a 33 Ohm
series termination.
N/C if not used
LPC encoded DMA/Bus master request.
Carrier Board:
Connect to
LPC - LDRQ0#, LDRQ1#
N/C if not used
ESPI Mode: eSPI pins used by eSPI slave to
request service from the eSPI master.
Carrier Board:
Connect to
eSPI Device – eSPI_ALERT0#, eSPI_ALERT1#.
N/C if not used
８７
I/O Note
O 3.3V
CMOS
O 1.8V 2
Suspend
/ 1.8V
I/O 3.3V
CMOS
I/O 1.8V 2
Suspend
/ 1.8V
I 3.3V Not all Modules
CMOS support LPC
DMA. Contact
your vendor for
information.
I 1.8V 2
Suspend
/ 1.8V