Advantech SOM-5992 Design Manual
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Advantech SOM-5992 Design Manual

Com express, come type7
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SOM-5992 COMe TYPE7
R1210 2018'09'25
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Summary of Contents for Advantech SOM-5992

  • Page 1 SOM-5992 COMe TYPE7 R1210 2018’09’25 ０...

  • Page 2: Table Of Contents

    2.3 General Purpose PCI Express Lanes ........... ２４ 2.3.1 General Purpose PCIe Signal Definitions ............２４ 2.3.2 PCI Express Lane Configurations – SOM-5992 Type 7 Limitations ....３４ 2.3.3 PCI Express General Routing Guidelines ............３６ 2.3.3.1 PCI Express Insertion Loss Budget with Slot Card ....... ３６...
  • Page 3 2.9.2 SATA Routing Guidelines ................８２ 2.9.2.1 General SATA Routing Guidelines ............８３ 2.9.3 SATA Trace Length Guidelines ............... ８５ 2.10 LPC and eSPI Interface *SOM-5992 is not support eSPI....８６ 2.10.1 LPC /eSPI Signal Definition ................８６ 2.10.2 LPC Routing Guidelines ................. ８９...
  • Page 4 2.14.2 Serial interface Routing Guidelines ..............１０７ 2.14.3 Serial interface Trace Length Guidelines ............１０７ 2.15 CAN Interface *SOM-5992 is not support CAN Interface....１０８ 2.15.1 CAN interface Signal Definitions ..............１０８ 2.15.2 CAN interface Routing Guidelines ..............１０９...
  • Page 5 Table 3: COM Express Type 7 Pin-out ..................１６ Table 4: General Purpose PCI Express Signal Descriptions ..........２４ Table 5: SOM-5992 PCI Express Lane Configurations ............３４ Table 6: PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board Slot Card ..３７...
  • Page 6 Table 33: BIOS Selection Straps ....................９７ Table 34: SPI Trace Length Guidelines ..................９９ Table 35: General Purpose I2C Interface Signal Descriptions .......... １０１ Table 36: I2C Trace Length Guidelines ................. １０２ Table 37: SMB Signal Definitions ................... １０４ Table 38: SMB Trace Length Guidelines................
  • Page 7 List of Figures Figure 1: SOM-5992 Block Diagram ....................１２ Figure 2: COM Express Type7 Connector Layout ..............１５ Figure 3: PCI Express Insertion Loss Budget with Slot Card ..........３６ Figure 4: PCI Express Insertion Loss Budget with Carrier Board PCIe Device ....３８...
  • Page 8 Figure 33: Topology for Serial interface ................１０７ Figure 34: Topology for CAN interface .................. １０９ Figure 35: Topology for SDIO ....................１１９ Figure 36: ATX Style Power Up Boot – Controlled by Power Button ........ １２２ Figure 37: AT Style Power Up Boot ..................１２３ ６...

  • Page 9: Introduction

    Type 7 Module. It includes Signal Descriptions, Routing Guidelines and Trace Length Guidelines. The main purpose is designing Carrier Board for helping customers fast and easy using the module of Advantech to be designed. 1.2 Acronyms / Definitions Table 1 : Acronyms / Definitions Signal Table Terminology Descriptions...
  • Page 10 Term Description Basic Module COM Express 125mm x 95mm Module form factor. BIOS Basic Input Output System – firmware in PC-AT system that is used to initialize system components before handing control over to the operating system. Baseboard Management Controller Controller-area network (CAN or CAN-bus) is a vehicle bus standard designed to allow microcontrollers to communicate with each other within a vehicle without a host computer.
  • Page 11 Term Description Low Pin-Count Interface: a low speed interface used for peripheral circuits such as Super I/O controllers, which typically combine legacy-device support into a single IC. Least Significant MDIO Management Data Input/Output, or MDIO, is a 2-wire serial bus that is used to manage PHYs or physical layer devices in media access controllers (MACs).
  • Page 12 Terminology Description Software-Definable Pin SGMII Serial Gigabit Media Independent Interface SM Bus System Management Bus SO-DIMM Small Outline Dual In-line Memory Module Serial Presence Detect – refers to serial EEPROM on DRAMs that has DRAM Module configuration information Serial Peripheral Interface Super I/O An integrated circuit, typically interfaced via the LPC bus that provides legacy PC I/O functions including PS2 keyboard and mouse ports, serial and...

  • Page 13: Reference Documents

    1.3 Reference Documents Document PICMGR COM.0 Revision 3.0 COM Express Base Specification, 2017’03’31 Final Intel EDS Document Intel Layout Guide Document ATX12V Power Supply Design Guide Rev. 2.01 1.4 Revision History Revision Date PCB Rev. Changes 0.10 2017’02’14 A101-1 1.00 2017’10’02 A101-2 1.

  • Page 14: Som-5992 Block Diagram

    1.5 SOM-5992 Block Diagram Figure 1 : SOM-5992 Block Diagram COM-Express R3.0 Type 7 DDR4 SO-DIMM 2DPC VR12.5 SO-DIMM x 4 (ECC) +VCORE DDR4 -1600, -1867, -2133, -2400 MT/s USB2[3:0] 4 x USB2.0 Max Capacity 64GB BDW-DE SATA[1:0] 2 x SATA Gen3...

  • Page 15: Module Pin-Out Types 7 - Required And Optional Features

    (Max) may be additionally implemented by a Module. Table 2 : Module Pin-out - Required and Optional Features Feature Type 7 Min / Max SOM-5992 System I/O PCI Express Lanes 0 - 5 6 / 6 PCI Express Lanes 6 - 15...
  • Page 16 Feature Type 7 Min / Max SOM-5992 Power Good 1 / 1 VCC_5V_SBY Contacts 4 / 4 Sleep Input 0 / 1 Lid Input 0 / 1 Carrier Board Fan Control 0 / 1 Power VCC_12V Contacts 24 / 24...

  • Page 17: Com Express Type 7 Interfaces

    2 COM Express Type 7 Interfaces 2.1 COM Express Type 7 Connector Layout Figure 2 : COM Express Type7 Connector Layout １５...

  • Page 18: Com Express Type 7 Connector Pin-Out

    2.2 COM Express Type 7 Connector Pin-out Table 3 : COM Express Type 7 Pin-out Connector Rows A and B Pin# Type 7 Description SOM-5992 Pin# Type 7 Description SOM-5992 Difference Difference GND(FIXED) GND(FIXED) GBE0_MDI3- GBE0_ACT# GBE0_MDI3+ LPC_FRAME#/ESPI_CS0# LPC_FRAME# GBE0_LINK100#...
  • Page 19 Connector Rows A and B Pin# Type 7 Description SOM-5992 Pin# Type 7 Description SOM-5992 Difference Difference RSVD I2C_CK BIOS_DIS0#/ESPI_SAFS BIOS_DIS0# I2C_DAT THRMTRIP# THRM# PCIE_TX13+ PCIE_RX13+ PCIE_TX13- PCIE_RX13- PCIE_TX12+ PCIE_RX12+ PCIE_TX12- PCIE_RX12- GND(FIXED) GND(FIXED) USB2- USB3- USB2+ USB3+ USB_2_3_OC# USB_0_1_OC#...
  • Page 20 Connector Rows A and B Pin# Type 7 Description SOM-5992 Pin# Type 7 Description SOM-5992 Difference Difference PCIE_TX0+ PCIE_RX0+ PCIE_TX0- PCIE_RX0- GND(FIXED) GND(FIXED) PCIE_TX8+ PCIE_RX8+ PCIE_TX8- PCIE_RX8- PCIE_TX9+ PCIE_RX9+ PCIE_TX9- PCIE_RX9- PCIE_TX10+ PCIE_RX10+ PCIE_TX10- PCIE_RX10- GND(FIXED) GND(FIXED) PCIE_TX11+ PCIE_RX11+ PCIE_TX11-...
  • Page 21 Connector Rows A and B Pin# Type 7 Description SOM-5992 Pin# Type 7 Description SOM-5992 Difference Difference A103 LID# B103 SLEEP# A104 VCC_12V B104 VCC_12V A105 VCC_12V B105 VCC_12V A106 VCC_12V B106 VCC_12V A107 VCC_12V B107 VCC_12V A108 VCC_12V B108...
  • Page 22 Connector Rows C and D Pin# Type 7 Description SOM-5992 Pin# Type 7 Description SOM-5992 Difference Difference GND(FIXED) GND(FIXED) USB_SSRX0- USB_SSTX0- USB_SSRX0+ USB_SSTX0+ USB_SSRX1- USB_SSTX1- USB_SSRX1+ USB_SSTX1+ USB_SSRX2- USB_SSTX2- USB_SSRX2+ USB_SSTX2+ GND(FIXED) GND(FIXED) USB_SSRX3- USB_SSTX3- USB_SSRX3+ USB_SSTX3+ 10G_PHY_MDC_SCL3 10G_PHY_MDIO_SDA3 10G_PHY_MDC_SCL2...
  • Page 23 Connector Rows C and D Pin# Type 7 Description SOM-5992 Pin# Type 7 Description SOM-5992 Difference Difference 10G_LED_SCL RSVD 10G_SFP_SDA1 10G_SFP_SCL1 10G_SFP_SDA0 10G_SFP_SCL0 10G_SDP0 10G_SDP1 GND(FIXED) GND(FIXED) 10G_KR_RX1+ 10G_KR_TX1+ 10G_KR_RX1- 10G_KR_TX1- 10G_PHY_MDC_SCL1 10G_PHY_MDIO_SDA1 10G_PHY_MDC_SCL0 10G_PHY_MDIO_SDA0 10G_INT0 10G_INT1 10G_KR_RX0+ 10G_KR_TX0+ 10G_KR_RX0-...
  • Page 24 Connector Rows C and D Pin# Type 7 Description SOM-5992 Pin# Type 7 Description SOM-5992 Difference Difference PCIE_RX22- PCIE_TX22- PCIE_RX23+ PCIE_TX23+ PCIE_RX23- PCIE_TX23- RSVD RSVD PCIE_RX24+ PCIE_TX24+ PCIE_RX24- PCIE_TX24- GND(FIXED) GND(FIXED) PCIE_RX25+ PCIE_TX25+ PCIE_RX25- PCIE_TX25- RSVD RSVD PCIE_RX26+ PCIE_TX26+ PCIE_RX26-...
  • Page 25 Connector Rows C and D Pin# Type 7 Description SOM-5992 Pin# Type 7 Description SOM-5992 Difference Difference C107 VCC_12V D107 VCC_12V C108 VCC_12V D108 VCC_12V C109 VCC_12V D109 VCC_12V C110 GND(FIXED) D110 GND(FIXED) ２３...

  • Page 26: General Purpose Pci Express Lanes

    2.3 General Purpose PCI Express Lanes The number of available PCI Express lanes varies with the Module Pin-out Type (refer to Section 2.3.2 'PCI Express Link Configuration '). If the Module supports off-Module x16 PCI Express Graphics, then PCI Express Lanes 16-31 shall be used to implement this. 2.3.1 General Purpose PCIe Signal Definitions Table 4 : General Purpose PCI Express Signal Descriptions Signal...
  • Page 27 Signal Pin# Description Note PCIE_RX2+ PCIe channel 2. Receive Input differential pair. I PCIE PCIE_RX2- Carrier Board: Device - Connect AC Coupling cap 0.1uF near COME to PCIE2 x1 device PETp/n0. Slot - Connect to PCIE2 x1 Conn pin A16, A17 PERp/n0.
  • Page 28 Signal Pin# Description Note PCIE_TX4+ PCIe channel 4. Transmit Output differential pair. O PCIE PCIE_TX4- Module has integrated AC Coupling Capacitor. Carrier Board: Device - Connect to PCIE4 x1 device PERp/n0. Slot - Connect to PCIE4 x1 Conn pin B14, B15 PETp/n0.
  • Page 29 Signal Pin# Description Note PCIE_RX7+ PCIe channel 7. Receive Input differential pair. I PCIE 1, 2 PCIE_RX7- Carrier Board: Device - Connect AC Coupling cap 0.1uF near to PCIE6 x1 device PETp/n0. Slot - Connect to PCIE6 x1 Conn pin A16, A17 PERp/n0.
  • Page 30 Signal Pin# Description Note PCIE_RX10+ PCIe channel 10. Receive Input differential pair. I PCIE PCIE_RX10- Carrier Board: Device - Connect AC Coupling cap 0.1/0.22uF near to PCIE device PETp/nX. N/C if not used. PCIE_TX10+ PCIe channel 10. Transmit Output differential pair. O PCIE PCIE_TX10- Module has integrated AC Coupling Capacitor.
  • Page 31 Signal Pin# Description Note PCIE_RX14+ PCIe channel 14. Receive Input differential pair. I PCIE PCIE_RX14- Carrier Board: Device - Connect AC Coupling cap 0.1/0.22uF near to PCIE device PETp/nX. N/C if not used. PCIE_TX14+ PCIe channel 14. Transmit Output differential pair. O PCIE PCIE_TX14- Module has integrated AC Coupling Capacitor.
  • Page 32 Signal Pin# Description Note PCIE_RX18+ PCIe channel 18. Receive Input differential pair. I PCIE PCIE_RX18- Carrier Board: Device - Connect AC Coupling cap 0.1/0.22uF near to PCIE device PETp/nX. N/C if not used. PCIE_TX18+ PCIe channel 18. Transmit Output differential pair. O PCIE PCIE_TX18- Module has integrated AC Coupling Capacitor.
  • Page 33 Signal Pin# Description Note PCIE_RX22+ PCIe channel 22. Receive Input differential pair. I PCIE PCIE_RX22- Carrier Board: Device - Connect AC Coupling cap 0.1/0.22uF near to PCIE device PETp/nX. N/C if not used. PCIE_TX22+ PCIe channel 22. Transmit Output differential pair. O PCIE PCIE_TX22- Module has integrated AC Coupling Capacitor.
  • Page 34 Signal Pin# Description Note PCIE_RX26+ PCIe channel 26. Receive Input differential pair. I PCIE PCIE_RX26- Carrier Board: Device - Connect AC Coupling cap 0.1/0.22uF near to PCIE device PETp/nX. N/C if not used. PCIE_TX26+ PCIe channel 26. Transmit Output differential pair. O PCIE PCIE_TX26- Module has integrated AC Coupling Capacitor.
  • Page 35 PCIE clocks output for more than one PCIE devices or slots. N/C if not used. Notes: 1. SOM-5992 Default : I210. 2. Only support PCIe Gen2. 3. The AC Coupling cap 0.1uF is used for Gen2 and 0.22uF is used for Gen3. ３３...
  • Page 36 2.3.2 PCI Express Lane Configurations – SOM-5992 Type 7 Limitations Table 5 : SOM-5992 PCI Express Lane Configurations B2B Pin Signal Link Width A68 PCIE_TX0+ B68 PCIE_RX0+ PCIE1X0 A69 PCIE_TX0- B69 PCIE_RX0- A64 PCIE_TX1+ B64 PCIE_RX1+ PCIE1X1 A65 PCIE_TX1- B65 PCIE_RX1-...
  • Page 37 D52 PCIE_TX16+ C52 PCIE_RX16+ PCIE16X0 D53 PCIE_TX16- C53 PCIE_RX16- D55 PCIE_TX17+ C55 PCIE_RX17+ PCIE16X1 D56 PCIE_TX17- C56 PCIE_RX17- D58 PCIE_TX18+ C58 PCIE_RX18+ PCIE16X2 D59 PCIE_TX18- C59 PCIE_RX18- D61 PCIE_TX19+ C61 PCIE_RX19+ PCIE16X3 D62 PCIE_TX19- C62 PCIE_RX19- D65 PCIE_TX20+ C65 PCIE_RX20+ PCIE16X4 D66 PCIE_TX20- C66 PCIE_RX20-...

  • Page 38: Pci Express General Routing Guidelines

    2.3.3 PCI Express General Routing Guidelines 2.3.3.1 PCI Express Insertion Loss Budget with Slot Card : PCI Express Insertion Loss Budget with Slot Card Figure 3 The module transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the module transmit path.

  • Page 39: Table 6: Pci Express Insertion Loss Budget, 1.25 Ghz With Carrier Board Slot Card

    Table 6 : PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board Slot Card Segment Loss (dB) Notes max. Length [mm/inches] 130/5.15 Allowance for 5.15 inches of module trace 3.45 dB loss @ 0.28 dB / GHz / inch and 1.66 dB crosstalk allowance. Coupling caps not included. Coupling 1.19 dB loss.

  • Page 40: Pci Express Insertion Loss Budget With Carrier Board Pcie Device

    Table 7 : PCI Express Insertion Loss Budget, 2.5 GHz with Carrier Board Slot Card Segment max. Length Notes [mm/inches] 127/5.0 Allowance for module trace. Coupling cap effects included within simulation. COM Express™ connector simulated at 2.5 GHz. 113/4.45 Allowance for Carrier Board. PCI Express Card slot connector simulated at 2.5 GHz.

  • Page 41: Table 8: Pci Express Insertion Loss Budget, 1.25 Ghz With Carrier Board Pcie Device

    Table 8 : PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board PCIe Device Segment Loss (dB) Notes max. Length [mm/inches] Allowance for 3.46 dB loss @ 0.28 dB / GHz / inch and 1.66 dB crosstalk 131/5.15 allowance. Coupling caps not included.

  • Page 42: Pci Express Trace Length Guidelines

    2.3.4 PCI Express Trace Length Guidelines Figure 5 : Topology for PCI Express Slot Card. Figure 6 : Topology for PCI Express Device Down. ４０...

  • Page 43: Table 10: Pci Express* Slot Card / Device Down Trace Length Guidelines

    11H (MS) and 3H(DS) Isolation to other signal groups 11H (MS) and 5H (DS) Tx/Rx Spacing 11H(MS) and 5H (DS) LA + LB Please see the SOM-5992 Layout Checklist Carrier Board Length Max length of LA+LB+LC Slot Card: 14” Device Down:4~ 16”...

  • Page 44: Nc-Si

    2.4 NC-SI 2.4.1 NC-SI Signal Definitions The NC-SI (‘Network Controller Sideband Interface’) is an electrical interface and protocol defined by the Distributed Management Task Force (DMTF), which enables the connection of a BMC (Baseboard Management Controller) to enable out-of-band remote manageability. If implemented, the NC-SI shall be assigned to the GBE0 interface.

  • Page 45: Nc-Si General Routing Guidelines

    NC-SI Single End 50Ω ±10% Nominal Trace Space within LPC Signal Group Spacing to Other Signal Group Please see the SOM-5992 Layout Checklist Carrier Board Length Max length of LA+LB 8.5” Single source Length matching between single ended signals Length matching between clock...

  • Page 46: 10Gb Ethernet

    2.5 10GB Ethernet 10GBASE-KR support was added to COM Express with revision 3.0 of the specification. Type 7 supports up to four 10GBASE-KR interfaces. The 10G MAC is located on the Module and the PHY is located on the Carrier. 10GBASE-KR uses a single transmit and a single receive ac coupled differential pair for data and a sideband bus for the PHY control and configuration.

  • Page 47: 10Gb Lan Signal Definitions

    2.5.1 10GB LAN Signal Definitions Table 13 : 10GB LAN Signal Description Signal Pin# Description Notes 10G_KR_TX0+ 10GBASE-KR port, transmit output differential pairs. O KR 10G_KR_TX0- Carrier board: Device - Connect AC Coupling cap 0.1uF near PHY. N/C if not used. 10G_KR_RX0+ 10GBASE-KR port, receive input differential pairs.
  • Page 48 Signal Pin# Description Notes MDIO Mode: Management Data I/O interface 10G_PHY_MDIO_SDA0 OC MOS 3.3V mode data signal for serial data transfers Suspend / between the MAC and an external PHY. 3.3V Carrier board: Device-Connect to PHY circuit. N/C if not used. I2C Mode: I2C data signal, of the 2-wire I/O OD CMOS...
  • Page 49 Signal Pin# Description Notes 10G_PHY_MDC_SCL1 MDIO Mode: Management Data I/O Interface OC MOS 3.3V mode clock signal for serial data transfers Suspend / between the MAC and an external PHY. 3.3V Carrier board: Device-Connect to PHY circuit. N/C if not used. I2C Mode: I2C Clock signal, of the 2-wire I/O OD CMOS...
  • Page 50 Signal Pin# Description Notes MDIO Mode: Management Data I/O interface 10G_PHY_MDIO_SDA3 OC MOS 3.3V mode data signal for serial data transfers Suspend / between the MAC and an external PHY. 3.3V Carrier board: Device-Connect to PHY circuit. N/C if not used. I2C Mode: I2C data signal, of the 2-wire I/O OD CMOS...
  • Page 51 Signal Pin# Description Notes 10G_PHY_CAP_23 PHY mode capability pin: Indicates if the PHY I CMOS 3.3V for 10G lanes 2 and 3 is capable of Suspend configuration by I2C. High indicates MDIO-only 3.3V configuration, and low indicates configuration capability via I2C or MDIO. The actual protocol used for PHY configuration is determined by the module, in part based on this input.
  • Page 52 Signal Pin# Description Notes 10G_SFP_SDA2 I2C data signal of the 2-wire management I/O OD CMOS interface used by the 10GbE controller to access 3.3V the management registers of an external Optical Suspend SFP Module. 3.3V Carrier board: 10G_SFP_SCL2 I2C clock signal of the 2-wire management I/O OD CMOS interface used by the 10GbE controller to access...
  • Page 53 I/O OD signals and PHY straps for I2C or MDIO operation CMOS of optical PHYs.Refer to the details in table 14 3.3V ‘I2C Data Mapping to Carrier Board based Suspend PCA9539 I/O expander‘ 3.3V Note: 1. SOM-5992 is NC. ５１...

  • Page 54: Table 14: I2C Data Mapping To Carrier Board Based Pca9539 I/O Expander

    Table 14 : I2C Data Mapping to Carrier Board based PCA9539 I/O expander Port Pin Signal Name Signal Function P0_0 10G_KR_LED0_0# PHY 0, LED 0 - STATUS/ACT P0_1 10G_KR_LED0_1# PHY 0, LED 1 - LINK SPEED MAX P0_2 10G_KR_LED0_2# PHY 0, LED 2 - LINK SPEED P0_3 10G_KR_LED1_0# PHY 1, LED 0 - STATUS/ACTIVITY...

  • Page 55: Example 10 Gb Ethernet Designs

    2.5.2 Example 10 GB Ethernet Designs 2.5.2.1 2016 Silicon 10GbE Fiber Implementation Figure 8: 10G Ethernet Design for Fiber PHY with Broadwell DE ５３...

  • Page 56: 2016 Silicon 10Gbe Copper Implementation

    2.5.2.2 2016 Silicon 10GbE Copper Implementation Figure 9: 10G Ethernet Design for Copper PHY with Broadwell DE ５４...

  • Page 57: Future Silicon 10Gbe Fiber Implementation

    2.5.2.3 Future Silicon 10GbE Fiber Implementation Figure 10: 10G Ethernet Design for Fiber PHY with Future SoC ５５...

  • Page 58: Future Silicon 10Gbe Copper Implementation

    2.5.2.4 Future Silicon 10GbE Copper Implementation Figure 11: 10G Ethernet Design for Copper PHY with Future SoC ５６...

  • Page 59: Ac Coupling Of 10G_Kr_Tx Signals

    2.5.3 AC Coupling of 10G_KR_TX Signals Situation A: Backplaned system (eg VPXR, CPCI, ..) Coupling is at receiver, in this case on both modules at receive pair. No coupling on carrier. Figure 12 : 10G Ethernet AC coupling – backplane system Situation B: Direct attached module-to-module connection.

  • Page 60: 10Gb Lan Routing Guidelines

    2.5.4 10GB LAN Routing Guidelines 10Gb Ethernet Insertion Loss Performance The 10Gb Ethernet interface to the COM Express connector is the KR interface as specified in the IEEE 802.3-KR Clause 72 and Annex 69B specification. This is the MAC to PHY interface as opposed to the PHY to connector (magnetic) interface of the 1Gb Ethernet connections.

  • Page 61: 10Gb Lan Kr Guidelines

    Isolation to equivalent pairs 12H (MS) and 5H(DS) Isolation to other signal groups 15H (MS) and 7H (DS) Tx/Rx Spacing 15H(MS) and 7H (DS) LA + LB SOM-5992 Layout Checklist Carrier Board Length Max length of LA+LB+LC Slot Card: 28” Device Down: 28”...

  • Page 62: 10Gb Lan Sideban Guidelines

    Nominal Trace Space within CRT Min. --10mils DAC Signal Group Spacing to Other Signal Group Min. --10mils Please reference SOM-5992 Layout check list Carrier Board Length Max length of LA+LB 8” Length matching Match the trace lengths within MDIO & MDC to ±250 mils.

  • Page 63: Gb Ethernet

    2.6 Gb Ethernet One Gigabit Ethernet port is defined, designated GBE0. The ports operate in 10, 100, or 1000 shall Mbit/sec modes. Magnetics are assumed to be on the Carrier Board. All COM Express Modules should implement at least one Ethernet port on the GBE0 pin slot and this be capable of at least 10/100 mode.
  • Page 64 Signal Pin# Description Note GBE0_MDI3+ Media Dependent Interface (MDI) differential pair I/O GBE GBE0_MDI3- 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Module has integrated termination. Carrier Board: Connect to Magnetics Module MDI3+/- N/C if not used GBE0_CTREF Reference voltage for Carrier Board Ethernet channel 0 GND min...

  • Page 65: Sdp Pins

    2.6.2 SDP Pins The Software Defined Pins (SDP) can be used to provide a timing communication path between the Module and Carrier. A board level signal that communicates time is a key element that facilitates clock synchronization between elements of a platform. Examples of such elements include, but are not limited to, CPU, Chipset, FPGA and others.

  • Page 66: Gb Ethernet Routing Guidelines

    2.6.3 Gb Ethernet Routing Guidelines 10/100/1000 Ethernet Insertion Loss Budget Figure 16 : 10/100/1000 Ethernet Insertion Loss Budget COM Express Ethernet implementations should conform to insertion loss values less than or equal to those shown in the table above. The insertion loss values shown account for frequency dependent material losses only.

  • Page 67: Gb Ethernet Trace Length Guidelines

    Spacing between digital ground Min. 60mils and analog ground plane (between the magnetics Module and RJ45 connector) Please see the SOM-5992 Layout Checklist Carrier Board Length; Max length of LA+LB COM Express Module to the magnetics Module - 5.0 inches.

  • Page 68: Reference Ground Isolation And Coupling

    2.6.5 Reference Ground Isolation and Coupling The Carrier Board should maintain a well-designed analog ground plane around the components on the primary side of the transformer between the transformer and the RJ-45 receptacle. The analog ground plane is bonded to the shield of the external cable through the RJ-45 connector housing. The analog ground plane should be coupled to the carrier’s digital logic ground plane using a capacitive coupling circuit that meets the ground plane isolation requirements defined in the 802.3-2005 specification.

  • Page 69: Usb2.0 Ports

    2.7 USB2.0 Ports shall All USB interfaces be USB 2.0 compliant. The minimum of 4 USB channels provides support for keyboard, mouse, CD/DVD drive, and one additional device. Up to four USB 2.0 ports support the extended signaling for SuperSpeed USB 3.0. USB0 optionally be configured as a USB client.
  • Page 70 Module USB client detect the presence of a USB host I 3.3V SUSPEND PRSNT on USB0. A high value indicates that a host is present. Carrier Board: 3.3V N/C if not used CMOS Notes: 1. SOM-5992 is NC pin. ６８...

  • Page 71: Usb Over-Current Protection (Usb_X_Y_Oc#)

    2.7.1.1 USB Over-Current Protection (USB_x_y_OC#) The USB Specification describes power distribution over the USB port, which supplies power for USB devices that are directly connected to the Carrier Board. Therefore, the host must implement over-current protection on the ports for safety reasons. Should the aggregate current drawn by the downstream ports exceed a permitted value, the over-current protection circuit removes power from all affected downstream ports.

  • Page 72: Usb2.0 Routing Guidelines

    2.7.2 USB2.0 Routing Guidelines USB 2.0 Insertion Loss Budget Figure 18 : USB 2.0 Insertion Loss Budget COM Express USB implementations should conform to insertion loss values less than or equal to those shown in the table above. The insertion loss values shown account for frequency dependent material losses only.

  • Page 73: Usb 2.0 General Design Considerations And Optimization

    2.7.2.1 USB 2.0 General Design Considerations and Optimization Use the following general routing and placement guidelines when laying out a new design. These guidelines help minimize signal quality and EMI problems. • Do not route USB 2.0 traces under crystals, oscillators, clock synthesizers, magnetic devices or ICs that use and/or duplicate clocks.

  • Page 74: Usb 2.0 Common Mode Chokes

    Figure 19 : USB 2.0 Good Downstream Power Connection 2.7.2.3 USB 2.0 Common Mode Chokes Testing has shown that common mode chokes can provide required noise attenuation. A design should include a common mode choke footprint to provide a stuffing option in the event the choke is needed to pass EMI testing.

  • Page 75: Emi / Esd Protection

    Common mode chokes distort full-speed and high-speed signal quality. As the common mode impedance increases the distortion increases, therefore test the effects of the common mode choke on full speed and high-speed signal quality. Common mode chokes with a target impedance of 80 Ω to 90 Ω, at 100 MHz, generally provide adequate noise attenuation.

  • Page 76: Usb2.0 Trace Length Guidelines

    Spacing between differential (MS) and (DS) pairs and low-speed non periodic signals Please see the SOM-5992 Layout Checklist Carrier Board Length Max length of LA+LB 16” Length matching Differential pairs (intra-pair): Max. ±2 mils Reference Plane...

  • Page 77: Usb3.0

    2.8 USB3.0 USB 3.0 is the third major revision of the Universal Serial Bus (USB) standard for computer connectivity. It adds a new transfer speed called SuperSpeed (SS) to the already existing LowSpeed (LS), FullSpeed (FS) and HighSpeed (HS). USB 3.0 leverages the existing USB 2.0 infrastructure by adding two additional data pair lines to allow a transmission speed up to 5 Gbit/s, which is 10 times faster than USB 2.0 with 480 Mbit/s.
  • Page 78 Signal Pin# Description Note USB_SSTX2+ USB Port 2, SuperSpeed TX + O PCIE USB_SSTX2- USB Port 2, SuperSpeed TX – Module has integrated AC Coupling Capacitors Carrier Board: Device - Connect to StdA_SSRX+/- Conn. - Connect 0Ω and 90Ω @100MHz USB3.0 Common Mode Choke(NL) combined in series and USB3.0 ESD suppressors to GND to Pin 9 StdA_SSTX+ / Pin 8 StdA_SSTX-, the value of CMC...
  • Page 79 Signal Pin# Description Note USB_SSRX1+ USB Port 1, SuperSpeed RX + I PCIE USB_SSRX1- USB Port 1, SuperSpeed RX – Carrier Board: Device - Connect AC Coupling Capacitors 100nF near COME to StdA_SSTX+/- Conn. - Connect 0Ω and 90Ω @100MHz USB3.0 Common Mode Choke(NL) combined in series and USB3.0 ESD suppressors to GND to Pin 6 StdA_SSRX+ / Pin 5 StdA_SSRX-, the value of CMC...

  • Page 80: Usb Over-Current Protection (Usb_X_Y_Oc#)

    2.8.1.1 USB Over-Current Protection (USB_x_y_OC#) The USB Specification describes power distribution over the USB port, which supplies power for USB devices that are directly connected to the Carrier Board. Therefore, the host must implement over-current protection on the ports for safety reasons. Should the aggregate current drawn by the downstream ports exceed a permitted value, the over-current protection circuit removes power from all affected downstream ports.

  • Page 81: Usb3.0 Routing Guidelines

    2.8.2 USB3.0 Routing Guidelines USB3.0 Insertion Loss Budget Figure 22 : USB3.0 Insertion Loss Budget Table 25 : USB3.0 Insertion Loss Budget Segment Loss (dB) Notes 1.94 Up to 3 inches of Module trace @ 2.5 GHz 1.20 COM Express connector at 2.5 GHz Up to 5 inches of Carrier Board trace @ 2.5 GHz with Common-Mode 3.64 Component...

  • Page 82: Usb3.0 Trace Length Guidelines

    Spacing between differential (MS) and (DS) pairs and low-speed non periodic signals Please see the SOM-5992 Layout Checklist Carrier Board Length Max length of LA+LB 10” Length matching Differential pairs (intra-pair): Max. ±2 mils Reference Plane...

  • Page 83: Sata

    2.9 SATA Support for up to two SATA ports is defined on the COM Express A-B connector. Support for a minimum of 0 port is required for Module Type 7. Serial ATA links for support of existing SATA-150 (revision 1.0, The COM 1.5Gb/s), SATA-300 (revision 2.0, 3Gb/s), and SATA-600 (revision 3.0, 6Gb/s) devices.

  • Page 84: Sata Routing Guidelines

    Signal Pin# Description Note SATA1_TX+ Serial ATA channel 1, Transmit output differential pair. O SATA SATA1_TX- Module has integrated AC Coupling capacitor Carrier Board: Connect to SATA1 Conn pin 2 TX+ Connect to SATA1 Conn pin 3 TX- N/C if not used. SATA_ACT# Serial ATA activity LED.

  • Page 85: General Sata Routing Guidelines

    Table 28 : SATA Insertion Loss Budge SATA Gen 1 Insertion Loss Budget, 1.5 GHz Segment Loss (dB) Notes 1.26 Up to 3.0 inches of module trace @ 0.28 dB / GHz / inch Coupling Caps 0.40 0.25 COM Express connector at 1.5 GHz measured value 3.07 Up to 7.2 inches of Carrier Board trace @ 0.28 dB / GHz / inch 6.00 Source specification cable and cable connector allowance...
  • Page 86 • For testability, route the TX and RX pairs for a given port on the same layer and close to each other to help ensure that the pairs share similar signaling characteristics. If the groups of traces are similar, a measure of RX pair layout quality can be approximated by using the results from actively testing the TX pair's signal quality.

  • Page 87: Sata Trace Length Guidelines

    Spacing between differential (MS) and (DS) pairs and low-speed non periodic signals Please see the SOM-5992 Layout Checklist Carrier Board Length Max length of LA+LB Support Gen3 : “2~5” Length matching Differential pairs (intra-pair): Max. ±5 mils...

  • Page 88: Lpc And Espi Interface *Som-5992 Is Not Support Espi

    2.10 LPC and eSPI Interface *SOM-5992 is not support eSPI. The Module LPC and eSPI interfaces share connector pins. A Module design support either LPC or eSPI or both, at the Module vendor’s discretion. Module pin ESPI_EN# is available for the shall Carrier to signal to the Module whether LPC or eSPI is to be used.
  • Page 89 Signal Pin# Description Note LPC_FRAME# LPC frame indicates start of a new cycle or O 3.3V termination of a broken cycle. CMOS Carrier Board: LPC - LFRAME# N/C if not used ESPI Mode: eSPI Master Chip Select Outputs ESPI_CS0# 1.8V Driving Chip Select0#.
  • Page 90 COM Express Module's BIOS in order to support basic initialization for those LPC devices. Otherwise the functionality of the LPC devices will not be supported by a Plug&Play or ACPI capable system. 2. SOM-5992 is not support eSPI. ８８...

  • Page 91: Lpc Routing Guidelines

    2.10.2 LPC Routing Guidelines 2.10.2.1 General Signals LPC signals are similar to PCI signals and may be treated similarly. Route the LPC bus as 50 Ω, single-ended signals. The bus may be referenced to ground (preferred), or to a well-bypassed power plane or a combination of the two.

  • Page 92: Espi Devices

    2.10.2.4 eSPI Devices At the time of this writing, the use case and design rules for eSPI are still being developed. Designers of Modules and Carriers are provided with the following guidance: shall not The maximum trace length for Carrier routed eSPI traces exceed 4.5”.

  • Page 93: Lpc Trace Length Guidelines

    50~55Ω ±10% Nominal Trace Space within LPC Min. 15mils Signal Group Spacing to Other Signal Group Min. 15mils Please see the SOM-5992 Layout Checklist Carrier Board Length Max length of LA+LB 23” Length matching between single Max. 250mils ended signals Length matching between clock Max.

  • Page 94: Spi - Serial Peripheral Interface Bus

    2.11 SPI – Serial Peripheral Interface Bus The SPI bus is used to support SPI-compatible flash devices. The SPI flash device can be up to 16 MB (128 Mb). The SPI bus is clocked at either 20 MHz, 25 MHz, 33 MHz or 50 MHz. SPI devices selected should support one of these frequencies.
  • Page 95 This signal is pulled to a logic high on the should module through a resistor. The Carrier only float this line or pull it low. please refer to Table33: BIOS Selection Straps. Carrier Board: 1 - N/C 0 - PD 1K to GND Note: 1. SOM-5992 is NC. ９３...
  • Page 96 SPI Power Introducing a SPI_POWER pin is desirable because some Module implementations will have the SPI power domain in power state S0 and others in S5. It is easier for Carrier Board designers to take the Carrier SPI power from a pin on the Module. The SPI_POWER voltage level was defined as 3.3V in COM.0 Rev.

  • Page 97: Bios Boot Selection

    2.11.2 BIOS Boot Selection For COM.0 R3, the Module Carrier based BIOS options have been expanded to support eSPI devices. A third pin that affects the BIOS location, named ESPI_EN#, works in conjunction with BIOS_DIS1# and BIOS_DIS0# to define the BIOS boot path. Additionally, the concepts of Master Attached Flash Sharing (MAFS) and Slave Attached Flash Sharing (SAFS) are introduced.

  • Page 98: Figure 28: Bios Selection Lpc Mode

    MAFS and SAFS BIOS Configurations Master Attached Flash Sharing (MAFS) is defined as the BIOS Flash directly attached to the processor SPI bus. Slave Attached Flash Sharing (SAFS) is defined as the BIOS Flash being attached behind a board Management Controller (BMC) or Embedded Controller (EC). MAFS and SAFS configurations apply to both LPC and eSPI enabled configurations.

  • Page 99: Table 33: Bios Selection Straps

    The A and, B notations in the figure26 above and the B, C, D and F notations in figure27 above are referenced in the table and text sections below. Note also that some of the features shown in these figures are mutually exclusive. Table 33 : BIOS Selection Straps Notes －...
  • Page 100 SPI BIOS MAFS Considerations – LPC Enabled The first four lines in Table 33 above are backwards compatible with the SPI BIOS options described in COM.0 Rev. 2, except that LPC FWH support is removed in COM.0 Rev 3. The LPC bus is enabled and is available for use on the Module or the Carrier for peripheral devices such as Board Management Controllers (BMC), Embedded Controllers (EC), Super I/O (SIO) or other general purpose devices.

  • Page 101: Spi Routing Guidelines

    50Ω ±10% Nominal Trace Space within SPI Min. 10mils Signal Group Spacing to Other Signal Group Min. 10mils Please see the SOM-5992 Layout Checklist Carrier Board Length Max length of LA+LB 6.5” SPI CLOCK to MOSI and CLOCK Max. 500mils...

  • Page 102: General Purpose I2C Bus Interface

    2.12 General Purpose I2C Bus Interface shall shall should The I2C port be available in addition to the SMBus. The I2C clock support 100kHz and shall support 400kHz operation. The maximum capacitance on the Carrier Board not exceed 100pF. The should I2C interface support multi-master operation.

  • Page 103: I2C Routing Guidelines

    Table 35 : General Purpose I2C Interface Signal Descriptions Signal Pin# Description Pwr Rail Note I2C_CK General Purpose I2C Clock output I/O OD 3.3V Carrier Board: CMOS Suspend 3.3VSB I2C device - Connect to SCL of I2C / 3.3V device. 3.3V I2C device - Connect 3.3V isolation circuit controlled by COME pin B24 PWR_OK to SCL of I2C device.

  • Page 104: I2C Trace Length Guidelines

    The maximum amount of capacitance allowed on the Carrier General Purpose I2C bus lines (I2C_DAT, I2C_CK) is specified by Advantech’s Module. The Carrier designer is responsible for ensuring that the maximum amount of capacitance is not exceeded and the rise/fall times of the signals meet the I2C bus specification.

  • Page 105: System Management Bus (Smbus)

    Module based devices. Typical Module located SMBus devices and their addresses include memory SPD (serial presence detect 1010 000x, 1010 001x), programmable clock synthesizes (1101 001x), clock buffers (1101 110x), thermal sensors (1001 000x), and management controllers (vendor defined address). Contact Advantech for information on the SMBus addresses used. １０３...

  • Page 106: Smb Signal Definitions

    2.13.1 SMB Signal Definitions Table 37 : SMB Signal Definitions Signal Pin# Description Pwr Rail Note SMB_CK System Management Bus bidirectional clock I/O OD 3.3V line CMOS Suspend Carrier Board: / 3.3V 3.3VSB SMBus device - Connect to SMBCLK of SMBus device. 3.3V SMBus device - Connect 3.3V isolation circuit controlled by COME pin B24 PWR_OK to SMBCLK of SMBus device.

  • Page 107: Smb Routing Guidelines

    The maximum load of SMBus lines is limited to 3 external devices. Please contact Advantech if more devices are required. Contact Advantech for a list of SMBus addresses used on the Module. Do not use the same address for Carrier located devices.

  • Page 108: General Purpose Serial Interface

    2.14. General Purpose Serial Interface Two TTL compatible two wire asynchronous serial ports are available on Module Types 7. This feature is introduced in COM.0 Revision 2 and uses pins on the A-B connector that have been re-claimed from the A-B VCC_12V pool.

  • Page 109: Serial Interface Routing Guidelines

    50Ω ±15% Nominal Trace Space within SPI Min. 10mils Signal Group Spacing to Other Signal Group Min. 15mils Please see the SOM-5992 Layout Checklist Carrier Board Length Max length of LA+LB Length Mismatch Via Usage Try to minimize number of vias Notes: １０７...

  • Page 110: Can Interface *Som-5992 Is Not Support Can Interface

    CAN protocol TX and RX signals from the Module into a differential half duplex line per the CAN specification. How the SER1 asynchronous lines are shared with CAN bus operation is Advantech specific. Advantech may choose to use the SER1 TX and RX lines to support asynchronous serial port operation, or CAN bus operation, or both, or neither.

  • Page 111: Can Interface Routing Guidelines

    Signal Group Spacing to Other Signal Group Min. 15mils SOM-5992 is not support CAN Interface Carrier Board Length Max length of LA+LB Length Mismatch Via Usage Try to minimize number of vias Notes: 1. SOM-5992 is not support CAN Interface １０９...

  • Page 112: Miscellaneous Signals

    2.16 Miscellaneous Signals 2.16.1 Miscellaneous Signals Table 43 : Miscellaneous Signal Definitions Signal Pin# Description Note TYPE0# The Type pins indicate the COM Express O 5V Only Available TYPE1# pin-out type of the Module. To indicate the on T2-T6 TYPE2# Module's pin-out type, the pins are either not 1.
  • Page 113 Signal Pin# Description Note LID# A103 LID switch. I 3.3V Low active signal used by the ACPI operating CMOS system for a LID switch. Carrier Board: R2/R3 Module only - Connect to LID button. N/C if not used. SLEEP# B103 Sleep button. I 3.3V Low active signal used by the ACPI operating CMOS...
  • Page 114 GPI1 / SDIO_DAT1 CMOS GPI2 / SDIO_DAT2 signals are pulled up by the Module. GPI3 / SDIO_DAT3 Carrier Board: Connect to GPI[3..0] N/C if not used VCC_RTC Real-time clock circuit power input. Nominally +3.0V Note: 1. SOM-5992 doesn’t support SDIO. １１２...

  • Page 115: Table 44: Signal Definition Sdio

    SDIO Data lines. These signals operate in push-pull I/O 3.3V SDIO_DAT1 / GPI1 mode. CMOS SDIO_DAT1 / GPI2 Carrier Board: SDIO_DAT1 / GPI3 Connect to DATA0-3 of SDIO/MMC device or card N/C if not used Note: 1. SOM-5992 doesn’t support SDIO. １１３...

  • Page 116: Power Management Signals

    2.16.2 Power Management Signals Signals PWR_OK, SYS_RESET#, and CB_RESET# shall be supported for all Module pinout types. Additionally, signal PWR_OK indicates that all the power supplies to the Module are stable within specified ranges and can be used to enable Module internal power supplies. PWR_OK has been traditionally used to hold off a Module startup to allow devices on the Carrier such as FPGAs to initialize.
  • Page 117 Signal Pin# Description Note PWR_OK Power OK from main power supply. A high value indicates I 3.3V that the power is good. This signal can be used to hold off CMOS Module startup to allow Carrier based FPGAs or other configurable devices time to be programmed.
  • Page 118 WAKE0# PCI Express wake up event signal. I 3.3V Module has integrated PU resistor to 3.3VDUAL Suspend Device - Connect to WAKE# pin of PCIE device. CMOS Slot - Connect to WAKE# pin B11 of PCIE slot. N/C if not used. WAKE1# General purpose wake-up signal.

  • Page 119: Rapid Shutdown * Som-5992 Is Not Support

    Description Note RAPID_SHUTD Trigger for Rapid Shutdown. Must be driven to 5V I 3.3V though a <=50 ohm source impedance for ≥ 20 μs. CMOS Carrier Board: 5.0V N/C if not used. Suspend/5.0V Note: 1. SOM-5992 is not support. １１７...

  • Page 120: Thermal Interface

    2.16.4 Thermal Interface Table 47 : Thermal Management Signal Definitions Signal Pin# Description Note THRM# Thermal Alarm active low signal generated by the I 3.3V external hardware to indicate an over temperature CMOS situation. This signal can be used to initiate thermal throttling.

  • Page 121: Sdio Signals Trace Length Guidelines

    Min. 15mils SOM-5992 doesn’t support SDIO. Carrier Board Length Max length of LA+LB ” Length matching Data/CMD to Clock must be matched within 200mils Reference Plane Continuous ground only Via Usage Max 2 vias Notes: 1. SOM-5992 don’t support SDIO. １１９...

  • Page 122: Reserved Pins

    2.17 Reserved Pins. RSVD pins are reserved for future use and should be no connect. But Advantech maybe use for another function, please see the 2.17.1 description. 2.17.1. Reserved Pins Definitions Table 49 : RSVD Definitions Signal Pin# Description Note RSVD Reserved pin.

  • Page 123: Power

    Basic format Modules are specified in COM.0 Rev. 3.x to support a power input range of 8.55V to 20.0V. Advantech offer a wide range input even on Compact and Basic Modules. COM Express Modules may consume significant amounts of power – 25 to 116W is common, and higher levels are allowed by the standard.

  • Page 124: Figure 36: Atx Style Power Up Boot - Controlled By Power Button

    Figure 36 : ATX Style Power Up Boot – Controlled by Power Button VCC_5V_SBY (To COMe) PWR_BTN# (To COMe) (Or other wake event) SUS_S3# (From COMe) Power Down PSON# (To ATX PS) VCC_12V (To COMe) VCC_5V, VCC3V For Carrier Board use (not needed by Module) PWR_OK (To COMe) Module Intermal Power Rails...

  • Page 125: Table 50: Power Management Timings

    Figure 37 : AT Style Power Up Boot Power Down VCC_5V_SBY (To COMe) (Optional) VCC_12V (To COMe) PWR_BTN# (To COMe) (Optional) SUS_S3# (From COMe) VCC_5V, VCC3V For Carrier Board use (not needed by Module) PWR_OK (To COMe) Module Intermal Power Rails SYS_RESET# (To COMe) (Optional) CB_RESET# (From COMe) Table 50 : Power Management Timings...
  • Page 126 Note: 1. There is a period of time (T6 in Figure 35 and Figure 36 above) during which the Carrier Board circuits have power but the COM Express Module main internal power rails are not up. This is because almost all COM Express internal rails are derived from the external VCC_12V and there is a non-zero start-up time for the Module internal power supplies.

  • Page 127: Design Considerations For Carrier Boards Containing Fpgas/Cplds

    3.3. Design Considerations for Carrier Boards containing FPGAs/CPLDs Very often, the Carrier Board will contain custom FPGA or other programmable devices which require the loading of program code before they are usable. The Carrier Board designer needs to take the necessary precautions to ensure that his Carrier Board logic is up and running before the Module starts.

  • Page 128: Electrical Characteristics

    4. Electrical Characteristics 4.1. Absolute Maximum Ratings Table 51 : Absolute Maximum Ratings SOM-5992 UNIT 8.5 (5-5%) 20(19+5%) Power 4.75 (5-5%) 5.25 (5+5%) RTC Battery 4.2. DC Characteristics Table 52 : DC Current Characteristics1 Intel D-1548 @2.0GHz (PTU) Power Plane...

  • Page 129: Inrush Current

    4.3. Inrush Current Table 54 : Inrush Current Power Plane Maximum Symbol G3 to S5 S5 to S0 +V5SB_CB 1.2708A ----- +VIN (+12V) ----- 2.54070A +VIN (+8.5V) ----- 3.2156A +VIN (+20V) ----- 1.7559A １２７...

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