I2C Trace Length Guidelines; Connectivity Considerations; Table 36: I2C Trace Length Guidelines; Figure 31: Topology For I2C - Advantech SOM-5992 Design Manual

2.12.3 I2C Trace Length Guidelines

Figure 31 : Topology for I2C
Table 36 : I2C Trace Length Guidelines
Parameter
Signal Group
Single End
Nominal Trace Space within I2C
Signal Group
Spacing to Other Signal Group
LA
LB
Max length of LA+LB
Length Mismatch
Via Usage
Notes:

2.12.4 Connectivity Considerations

The maximum amount of capacitance allowed on the Carrier General Purpose I2C bus lines (I2C_DAT,
I2C_CK) is specified by Advantech's Module. The Carrier designer is responsible for ensuring that the
maximum amount of capacitance is not exceeded and the rise/fall times of the signals meet the I2C bus
specification. As a general guideline, an IC input has 8pF of capacitance, and a PCB trace has 3.8pF per
inch of trace length.
Main Route Guidelines
I2C
50Ω ±15%
Min. 10mils
Min. 10mils
Please see the SOM-5992 Layout Checklist
Carrier Board Length
ASPA
NA
Try to minimize number of vias
１０２
Notes