Lpc Routing Guidelines; General Signals; Bus Clock Routing; Carrier Board Lpc Devices - Advantech SOM-5992 Design Manual

2.10.2 LPC Routing Guidelines

2.10.2.1 General Signals

LPC signals are similar to PCI signals and may be treated similarly. Route the LPC bus as 50 Ω,
single-ended signals. The bus may be referenced to ground (preferred), or to a well-bypassed power
plane or a combination of the two. Point-to-point (daisy-chain) routing is preferred, although stubs up to
1.5 inches may be acceptable. Length-matching among LPC_AD[3:0], LPC_FRAME# are needed

2.10.2.2 Bus Clock Routing

Route the LPC clock as a single-ended, 50 Ω trace with generous clearance to other traces and to itself.
A continuous ground-plane reference is recommended. Routing the clock on a single ground referenced
internal layer is preferred to reduce EMI.
The LPC clock implementation should follow the routing guidelines for the PCI clock defined in the COM
Express specification and the 'PCI Local Bus Specification Revision 2.3'.

2.10.2.3 Carrier Board LPC Devices

should
Carrier Board LPC devices be clocked with the LPC clock provided by the Module interface. If the
should
Carrier Board has two loads on the LPC clock these loads be connected to the common clock
should
without a buffer. The Carrier Board not have more than two loads on the LPC clock.
should
Carrier Board LPC devices be reset with signal CB_RESET#.
A typical routing topology for a Module LPC device and two Carrier Board LPC devices clock is shown
below. This topology is used by Modules that start and stop the LPC clock on the fly. In this case, a
buffer cannot be used and all LPC devices must share a common clock.
Figure 26 : Typical routing topology for a Module LPC device
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