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IP 240
Setpoint reached
or error has
occured
Status bit is updated
Interrupt is generated
Output is set
Output is reset
Fig. 12-3. Response Time for Evaluation of the Actual Value and of Wirebreak
IN/GT input
Status bit is updated
Interrupt IRx is generated
Output is switched
Fig. 12-4. Response Time for Evaluation of Inputs IN and GT
Note
Switching of the IP outputs is
•
firmware-controlled in position decoding and positioning mode.
•
counter chip controlled in counting mode and thus independent of the module
firmware's response time.
EWA 4NEB 811 6120-02a
Position decoding and positioning
modes
1)
t
t
reak
1
t
=max. 50 µs (when ohmic load and I
1
1) Is reset following reading of the interrupt request bytes
and Zero Mark Errors
Position decoding and positioning
modes
1)
t
t
reak
1
t
reak
t
=max. 50 µs (when ohmic load and I
1
1) Is reset following reading of the interrupt request bytes
t
1
=50 mA)
output
Counting
t
1
t
1
t
reak
=50 mA)
output
Response Times
Counting
mode
1)
t
reak
mode
t
reak
12-3
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