Table of Contents
Advertisement
IP 240
10.13.3 Synchronization with an External Control Signal
When synchronization with an external control signal, referred to from here on as "cyclic
synchronization", is used, the IP 240 evaluates the edge change at the IN input.
On a positive signal edge (signal change from 0 to 1) at this input, the actual value is set to the
value of the zero offset and the position last selected reactivated.
On a negative signal edge (signal change from 1 to 0) at this input, the current actual value is
stored in a final value register.
Since normal actual value acquisition takes place in parallel to the evaluation of the edge change
at the IN input, positioning is also possible in this synchronization mode.
The ZYSY control bit
Cyclic synchronization is selected via the ZYSY control bit. This bit is evaluated on an edge-
triggered basis.
The first time ZYSY=1 is transferred,
•
the SYNC bit is reset.
•
range bits BEE1 to 3 and direction bit RICH are set to "1", as the position number last selected
was invalidated, and
•
the channel's outputs are disabled.
When you select cyclic synchronization you can also specify a new position number; the new
position number, however, does not go into force until there is a positive signal edge at the
IN input.
Refer to Section 10.14.1 for information on selecting a position number.
To exit cyclic synchronization, you must transfer ZYSY=0 to the IP 240. This does not affect any
synchronization currently in progress.
Evaluating the IN signal
When you select cyclic synchronization, a positive-going edge at the IN input initiates the
following on the IP 240:
•
The actual value is set to the value of the zero offset
•
Synchronization bit SYNC is set
•
The position last transferred is immediately reactivated and
•
In dependence on the current actual value,
- range bits BEE1 to 3 and RICH are updated,
- the enabled outputs are set and
- the interrupts configured for the active position are generated.
The following steps are initiated on a negative-going signal edge at the IN input:
•
The current actual value is stored in a final value register.
You can read this final value from the IP together with the actual value ( Section 10.16).
•
Status bit MESE (measuring terminated) is set to show that the final value was stored.
•
The interrupt allocated to status bit MESE is generated and the MES bit set in the interrupt
request bytes.
•
A check is made to see whether or not the final value has been read out from the IP.
If it has not, status bit UEBS (Overwrite) is set.
•
The interrupt allocated to status bit UEBS is generated and the UBS bit set in the interrupt
request bytes.
Note
If the IN signal was already active when cyclic synchronization was selected, no
synchronization takes place. The subsequent negative-going edge is not evaluated.
EWA 4NEB 811 6120-02a
Positioning
10-47
Advertisement
Table of Contents
