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IP 240
12
Response Times
The response time is the time between reaching of a setpoint and the IP 240's reaction.
The signals from the incremental encoders or pulse encoders are acquired by counter chips. These
counter chips make an internal count available which is read and evaluated in each module
firmware (FW) cycle. IP inputs IN and GT are also sensed at the hardware level and postprocessed
by the firmware.
All evaluations in which the IP 240 firmware is involved are, as regards their response time,
determined by the cycle time of the module firmware. The cycle time itself depends on:
•
the modes in which the channels are operated,
• the configuring data,
• the current actual value and
• the requests for data interchange with the S5 CPU.
12.1
Structure of a Firmware Cycle
A firmware cycle is subdivided into slices for
•
processing of channel 1
•
processing of channel 2
•
data interchange
When processing of a channel begins, the data acquired at the hardware level is read in by the
firmware. Because the IP 240 firmware has a free-wheeling cycle, this is not done in a fixed time-
slot pattern, but rather is dependent on the processing times of the slices for "Processing of
channel 1", "Processing of channel 2" and "Data interchange with the S5 CPU".
No more than one data interchange with the S5 CPU may take place in a firmware cycle. Once
new data have been transferred to the IP 240, the next FW cycle is closed to data interchange.
A pending request is processed as soon as possible. The data interchange can thus be carried out
at different points within the firmware cycle.
The data made available by the IP 240 is always based on the last count read, and is not updated
again when a data interchange takes place.
EWA 4NEB 811 6120-02a
Start
End
of a FW cycle
Data interchange with the S5 CPU
Processing of channel 1
Figure 12-1. Structure of a Firmware Cycle (Example)
Processing of channel 2
Response Times
12-1
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